A scheme that modulates the training sequence is proposed to support two-layer data streams in the time domain synchronous orthogonal frequency division multiplex (TDS-OFDM) systems. A theoretical analysis and computer simulation show that the proposed scheme works well and that the two layer data streams are compatible with each other.

There is no clear criterion yet for evaluating wipers based on performances of wiping raindrops and visibility in forward view. In the visibility evaluation in rainy driving, it is important to examine spatial frequency and contrast of objects in forward view. Spatial frequency and contrast of image which were affected by raindrops are calculated based on them of background board which were printed stripe patterns. Variations with time of power of analysed frequency and decreased contrast are synchronized with motion of the wiper for the all experimental cases. Moreover, we executed questionnaire, and evaluated the view of the background board. These results show that the proposed methods have been validated in evaluation with wiping performance.

For advanced mobile communication systems that adopt orthogonal frequency-division multiple access (OFDMA) technologies, intercarrier interference (ICI) significantly degrades performance when mobility is high. Standard specifications and concerns about complexity demand low-cost methods with deployment readiness and decent performance. In this paper, novel zero forcing (ZF) and minimum mean-square error (MMSE) equalizers based on per-subcarrier adaptive (PSA) processing and perturbation-based (PB) approximation are introduced. The proposed equalizers strike a good balance between implementation cost and performance; therefore they are especially suitable for OFDMA downlink receivers. Theoretical analysis and simulations are provided to verify our claims.

A wideband beamformer with mainlobe control is proposed. To make the beamformer robust against pointing errors, inequality rather than equality constraints are used to restrict the mainlobe response, thus more degrees of freedom are saved. The constraints involved are nonconvex, therefore are linearly approximated so that the beamformer can be obtained by iterating a second-order cone program. Moreover, the response variance element is introduced to achieve a frequency invariant beamwidth. The effectiveness of the technique is demonstrated by numerical examples.

For maximum-likelihood (ML) estimation to jointly track carrier frequency offset (CFO) and channel impulse response (CIR) in orthogonal frequency division multiplexing (OFDM) systems, we present a finite high order approximation method utilizing the MATLAB ‘roots' command on the log-likelihood function derived from the OFDM received signal, coupled with an adaptive iteration algorithm. The tracking performance of this high order approximation algorithm is found to be excellent, and as expected, the algorithm outperforms the other existing first order approximation algorithms.

This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

This paper addresses conjugate-gradient (CG) based pilot-assisted channel estimation and equalization in doubly selective channels for orthogonal frequency division multiplexing (OFDM) block transmissions. With the help of the discrete prolate spheroidal sequence, which shows flat mean-square error (MSE) curves for the reconstructed channels in the presence of Doppler frequency mismatch, a basis expansion model for a parsimonious channel representation over multiple OFDM blocks is developed, a system equation for the least square channel estimation under widely used pilot lattices, where the pilot symbols are irregularly placed in the subcarrier domain, is formulated by introducing carving matrices, and the standard CG method is applied to the system. Relying on the CG method again, the linear minimum mean-square error channel equalization is pursued without performing any matrix inversion, while elevating the convergence speed of the iterative algorithm with a simple preconditioner. Finally, we validate our schemes with numerical experiments on the integrated services digital broadcasting-terrestrial system in doubly-selective channels and determine the normalized MSE and uncoded bit error rate.

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18 µm technology, the core area of the processor is 3.47 mm2 and the maximum operating frequency can be up to 500 MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

A novel watermarked MDC system based on the SFQ algorithm and the sub-sampling method is proposed in this paper. Sub-sampling algorithm is applied onto the transformed image to introduce some redundancy between different channels. Secret information is embedded into the preprocessed sub-images. Good performance of the new system to defense the noise and the compression attacks is shown in the experimental results.

The periodogram scheme is a versatile method for large frequency offset estimation which requires preambles, in general, and only a few reference signals. However, the drawback of the conventional scheme is its inaccuracy in detecting the integer part of frequency offset which dominates the accuracy of frequency offset estimation. In order to increase the accuracy of the estimation, we directly interpolate a coefficient of the periodogram. The conventional periodogram and proposed schemes are compared in terms of the mean square error performance in the long term evolution system. The performance of the proposed method is compared with the conventional one and the simulation results indicate the better performance of the proposed one.

This letter presents a robust receiver using the generalized sidelobe canceller aided with the high-order derivative constraint technique for multicarrier code-division multiple-access (MC-CDMA) uplink against carrier frequency offset (CFO). Numerical results demonstrate the efficacy of the proposed receiver.

This letter presents a novel opportunistic cooperative positioning approach for orthogonal frequency-division multiple access (OFDMA) systems. The basic idea is to allow idle mobile terminals (MTs) opportunistically estimating the arrival timing of the training sequences for uplink synchronization from active MTs. The major advantage of the proposed approach over state-of-the-arts is that the positioning-related measurements among MTs are performed without the paid of training overhead. Moreover, Cramer-Rao lower bound (CRLB) is utilized to derive the positioning accuracy limit of the proposed approach, and the numerical results show that the proposed approach can improve the accuracy of non-cooperative approaches with the a-priori stochastic knowledge of clock bias among idle MTs.

The non-reference method is widely useful to estimation picture quality on the decoder side. In this paper, we discuss the estimation method for spatial blur that divides the frequency zones by the absolute value of 64 coefficients with an 8-by-8 DCT and compares them. It is recognized that absolute blur estimation is possible with the decoded picture only.

In this paper, we propose low complexity channel parameter tracking methods for adaptive OFDM MMSE channel estimation. Even though the MMSE estimation is one of the most accurate channel estimation methods, it requires several channel information including Doppler frequency, RMS (root mean squared) delay spread, and SNR. To implement the MMSE estimation, tracking of such parameters should be preceded. We propose methods to track the above 3 channel parameters. As for Doppler frequency estimation, we propose an extremum method with a parabolic model, which is a key contribution of this paper. We also analyze the computational complexity of the proposed algorithms. Simulations show that the proposed tracking algorithm tracks the parameters well, and performs better than the conventional fixed-parameter algorithm in terms of BER performance. The BER performance of the adaptive MMSE estimation is better than that of a fixed-parameter (robust) MMSE estimator by about 5 dB.

We propose a methodology of loop design optimization for fourth-order fractional-N phase locked loop (PLL) frequency synthesizers featuring a short settling time of 5 µsec for applications in an active RFID (radio frequency identification) and automobile smart-key systems. To establish the optimized design flow, equations presenting the relationship between the specification and PLL loop parameters in terms of settling time, loop bandwidth, phase margin, and phase noise are summarized. The proposed design flow overcomes the settling time inaccuracy in conventional second-order approximation methods by obtaining the accurate relationship between settling time and loop bandwidth with the MATLAB Control System Toolbox for the fourth-order PLLs. The proposed flow also features the worst-case design by taking account of the process, voltage, and temperature (PVT) variations in loop filter components, and considers the tradeoff between phase noise and area. The three-step optimization process consists of 1) the derivation of the accurate relationship between the settling time and loop bandwidth for various PVT conditions, 2) the derivation of phase noise and area as functions of area-dominant filter capacitance, and 3) the derivation of all PLL loop components values. The optimized design result is compared with circuit simulations using an actually designed fourth-order fractional-N PLL in a 1.8 V 0.18 µm CMOS technology. The error between the design and simulation for the setting time is reduced from 0.63 µsec in the second-order approximation to 0.23 µsec in the fourth-order optimization that proves the validity of the proposed method for the high-speed settling operations.

This paper proposes a comb filter design method which utilizes two linear phase FIR filters for flexibly adjusting the comb filter's frequency response. The first FIR filter is used to individually adjust the notch gains, which denote the local minimum gains of the comb filter's frequency response. The second FIR filter is used to design the elimination bandwidths for individual notch gains. We also derive an efficient comb filter by incorporating these two FIR filters with an all-pass filter which is used in a conventional comb filter to accurately align the nulls with the undesired harmonic frequencies. Several design examples of the derived comb filter show the effectiveness of the proposed comb filter design method.

Reduction of the intensity noise in semiconductor lasers is an important subject for the higher performance of an application. Simultaneous usage of the superposition of high frequency current and the electric negative feedback loop was proposed to suppress the noise for the higher power operation of semiconductor lasers. Effective noise reduction of more than 25 dB with 80 mW operation was experimentally demonstrated.

This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.