High-performance computing (HPC) has penetrated into various research fields, yet the increase in computing power is limited by conventional electrical interconnections. The proposed architecture, NEST, exploits wavelength routing in arrayed waveguide grating routers (AWGRs) to achieve a scalable, low-latency, and high-throughput network. For the intra pod and inter pod communication, the symmetrical topology of NEST reduces the network diameter, which leads to an increase in latency performance. Moreover, the proposed architecture enables exponential growth of network size. Simulation results demonstrate that NEST shows 36% latency improvement and 30% throughput improvement over the dragonfly on an average.

This paper describes the design and experiment results of a 25Gbps vertical-cavity surface emitting laser (VCSEL) driver circuit for a multi channel optical transmitter. To compensate for the non-linearity of the VCSEL and achieve high speed data rate communication, an asymmetric pre-emphasis technique is proposed for the VCSEL driver. An asymmetric pre-emphasis signal can be created by adjusting the duty ratio of the emphasis signal. The VCSEL driver adopts a double cascode connection that can apply a drive current from a high voltage DC bias and feed-forward compensation that can enhance the band-width for common-cathode VCSEL. For the design of the optical module structure, a two-tier low temperature co-fired ceramics (LTCC) package is adopted to minimize the wire bonding between the signal pad on the LTCC and the anode pad on the VCSEL. This structure and circuit reduces the simulated deterministic jitter from 12.7 to 4.1ps. A test chip was fabricated with the 65-nm standard CMOS process and demonstrated to work as an optical transmitter. An experimental evaluation showed that this VCSEL driver with asymmetric pre-emphasis reduced the total deterministic jitter up to 8.6ps and improved the vertical eye opening ratio by 3% compared with symmetric pre-emphasis at 25Gbps with a PRBS=29-1 test signal. The power consumption of the VCSEL driver was 3.0mW/Gbps/ch at 25Gbps. An optical transmitter including the VCSEL driver achieved 25-Gbps, 4-ch fully optical links.

This paper covers new architectures, technologies, and performance benchmarking together with prospects for high productivity and high performance computing enabled by photonics. The exponential and sustained increases in computing and data center needs are driving the demands for exascale computing in the future. Power-efficient and parallel computing with balanced system design is essential for reaching that goal as should support ∼billion total concurrencies and ∼billion core interconnections with ∼exabyte/second bisection bandwidth. Photonic interconnects offer a disruptive technology solution that fundamentally changes the computing architectural design considerations. Optics provide ultra-high throughput, massive parallelism, minimal access latencies, and low power dissipation that remains independent of capacity and distance. In addition to the energy efficiency and many of the fundamental physical problems, optics will bring high productivity computing where programmers can ignore locality between billions of processors and memory where data resides. Repeaterless interconnection links across the entire computing system and all-to-all massively parallel interconnection switch will significantly transform not only the hardware aspects of computing but the way people program and harness the computing capability. This impacts programmability and productivity of computing. Benchmarking and optimization of the configuration of the computing system is very important. Practical and scalable deployment of photonic interconnected computing systems are likely to be aided by emergence of athermal silicon photonics and hybrid integration technologies.

A new wavelength-selective optical modulator was proposed and discussed. The modulator consists of three kinds of distributed Bragg reflectors (DBRs) integrated in a single straight waveguide. The waveguide can guide TE$_0$ and TE$_1$ modes, and an in-line Michelson interferometer is constructed by the three DBRs. An operation-wavelength wave among incident wavelength-division-multiplexed TE$_1$ guided waves is split into TE$_0$ and TE$_1$ guided waves by one of DBRs, and combined by the same DBR to be TE$_0$ output wave with interference after one of waves is phase-modulated. A modulator using an electro-optic (EO) polymer is designed, and the static performance was predicted theoretically. An operation principle was confirmed experimentally by a prototype device utilizing a thermo-optic effect instead of the EO effect.

We describe 25-Gb/s error-free transmission over multi-mode fiber (MMF) by using a transmitter based on a 1.3-µm lens-integrated surface-emitting laser (LISEL) and a CMOS laser-diode driver (LDD). It demonstrates 25-Gb/s error-free transmission over 30-m MMF under the overfilled-launch condition and over 150-m MMF with a power penalty less than 1.0 dB under the underfilled-launch condition.

We demonstrate the wavelength trimming of MEMS VCSELs by etching a cantilever-shaped top mirror using FIB etching. The proposed technique can be used for the post-process precise wavelength allocation of athermal MEMS VCSELs. The modeling and experimental results on 850 nm MEMS VCSELs are presented. The results show a possibility of realizing both red-shift and blue-shift wavelength changes by choosing the etching area of the cantilever.

The element-by-element finite element method (EBE-FEM) combined with the preconditioned conjugate gradient (PCG) technique is employed in this paper to calculate the coupling capacitances of multi-level high-density three-dimensional interconnects (3DIs). All capacitive coupling 3DIs can be captured, with the effects of all geometric and physical parameters taken into account. It is numerically demonstrated that with this hybrid method in the extraction of capacitances, an effective and accurate convergent solution to the Laplace equation can be obtained, with less memory and CPU time required, as compared to the results obtained by using the commercial FEM software of either MAXWELL 3D or ANSYS.

A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A=2(L(CT+0.5C))1/2/(RT(CT+CJ)+RTC+RCT+0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.

This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.

This work proposes a new method for RLCG interconnect model-order reductions in consideration with the adjoint network. Relationships between an original MNA network and its corresponding adjoint MNA network will be explored first. It will be shown that the congruence transformation matrix used in the one-sided projection can be constructed by using the bi-orthogonal bases developed from the Lanczos-type algorithms. In particular, if the multi-port driving-point impedance of RLCG interconnect circuits is the main concern, the transfer functions and system moments of the adjoint network can be directly calculated from those of the original RLCG interconnect network by exploring symmetric properties of the MNA formulation. Therefore, the cost of constructing the congruence transformation matrix can be simplified by up to 50% of the previous methods. Comparative studies among various standard methods and the proposed methods are also investigated. Experimental results on large-scale RLCG interconnect circuits will demonstrate the accuracy and the efficiency of the proposed method.

This paper presents a systematic methodology for the system-level assessment of signal integrity and electromagnetic compatibility effects in high-speed communication and information systems. The proposed modeling strategy is illustrated via a case study consisting of a critical coupled net of a complex system. Three main methodologies are employed for the construction of accurate and efficient macromodels for each of the sub-structures typically found along the signal propagation paths, i.e. drivers/receivers, transmission-line interconnects, and interconnects with a complex 3D geometry such as vias and connectors. The resulting macromodels are cast in a common form, enabling the use of either SPICE-like circuit solvers or VHDL-AMS equation-based solvers for system-level EMC predictions.

A method is proposed to compute moments of distributed coupled RLC interconnects. Both uniform line models and non-uniform line models will be developed. Considering both self inductances and mutual inductances in multi-conductors, recursive moment computations formulae of lumped coupled RLC interconnects are extended to those of distributed coupled RLC interconnects. By using the moment computation technique in conjunction with the projection-based order reduction method, the inductive crosstalk noise waveform can be accurately and efficiently estimated. Fundamental developments of the proposed approach will be described. Simulation results demonstrate the improved accuracy of the proposed method over the traditional lumped methods.

In this paper, we propose a new algorithm for calculating the exact poles of the admittance matrix of RLCG interconnects. After choosing dominant poles and corresponding residues, each element of the exact admittance matrix is approximated by partial fraction. A procedure to obtain the residues that guarantee the passivity is also provided, based on experimental studies. In the procedure the residues are calculated by using the least squares method so that the partial fraction matches each element of the exact admittance matrix in the frequency-domain. From the partial fraction representation, the asymptotic equivalent circuit models which can be easily simulated with SPICE are synthesized. It is shown that an efficient model-order reduction is possible for short-length interconnects.

This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.

A novel method is presented to compute moments of high-speed VLSI interconnects, which are modeled as coupled RLC trees. Recursive formulae of moments of coupled RC trees are extended to those for coupled RLC trees by considering both self inductances and mutual inductances. Analytical formulae for voltage moments at each node are derived explicitly. The formulae can be efficiently used for estimating delay and crosstalk noise. The inductive crosstalk noise waveform can be accurately and efficiently estimated using the moment computation technique in conjunction with the projection-based order reduction method. Fundamental aspects of the proposed approach are described in details. Experimental results show the increased accuracy of the proposed method over that of the traditional ones.

We present a new and efficient approach for extracting on-chip mutual inductances of VLSI interconnects by applying approximation formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of the bars, the model is sufficiently accurate for the interconnections of current and future LSIs because the skin and proximity effects do not affect most wires. Expression of the equations in polynomial form provides a balance between accuracy and computational complexity. These equations are mapped according to the geometric structures for which they are most suitable in minimizing the runtime of inductance calculation while retaining the required accuracy. Within geometrical constraints, the wires are of arbitrary specification. Results of a comprehensive evaluation based on the ITRS-specified global wiring structure for 2003 shows that the inductance values were extracted by using the proposed approach, and they were within several percent of the values obtained by using commercial three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design that has 300-k interconnecting segments.

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.

IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.

A new algorithm, which is incorporated into the waveform relaxation analysis, for efficiently simulating the transient response of single lossy transmission lines or lossy coupled multiconductor transmission lines, terminated with arbitrary networks will be presented. This method exploits the inherent delay present in a transmission line for achieving simulation efficiency equivalent to obtaining converged waveforms with a single iteration by the conventional iterative waveform relaxation approach. To this end we propose 'line delay window partitioning' algorithm in which the simulation interval is divided into sequential windows of duration equal to the transmission line delay. This window scheme enables the computation of the reflected voltage waveforms accurately, ahead of simulation, in each window. It should be noted that the present window partitioning scheme is different from the existing window techniques which are aimed at exploiting the non–uniform convergence in different windows. In contrast, the present window technique is equivalent to achieving uniform convergence in all the windows with a single iteration. In addition our method eliminates the need to simulate the transmission line delay by the application of Branin's classical method of characteristics. Further, we describe a simple and efficient method to compute the attenuated waveforms using a particular form of lumped element model of attenuation function. Simulation examples of both single and coupled lines terminated with linear and nonlinear elements will be presented. Comparison indicates that the present method is several times faster than the previous waveform relaxation method and its accuracy is verified by the circuit simulator PSpice.

In this paper, we present some novel concepts and photonic devices for use in optical interconnects. First, we review the progress of surface emitting lasers while featuring materials and performances including thresholds, power output, RIN, linewidth, and so on. Advanced technology for aiming at spontaneous emission control, photon recycling, polarization control, wavelength tuning, integration etc. will be considered. Then we touch on some other possible devices for optical interconnects. Lastly, we discuss on lightwave subsystems applying these devices and concepts.