This paper proposes a method for reducing the peak-to-average power ratio (PAPR) at the output signal of a digital predistortion linearizer (DPDL) that compensates for frequency dependent intermodulation distortion (IMD) components. The proposed method controls the amplitude and phase values of the frequency components corresponding to the transmission bandwidth of the output signal. A DPDL employing the proposed method simultaneously provides IMD component cancellation of out-of-band components and PAPR reduction at the output signal. This paper identifies the amplitude and phase conditions to minimize the PAPR. Experimental results based on a 2-GHz band 1-W class power amplifier show that the proposed method improves the drain efficiency of the power amplifier when degradation is allowed in the error vector magnitude. To the best knowledge of the authors, this is the first PAPR reduction method for DPDL that reduces the PAPR while simultaneously compensating for IMD components.

A new low-power feedback structure for a power amplifier (PA) reduces signal distortion while keeping the power efficiency of the PA high. The feedback structure injects the envelope of the third-order harmonics into the input signal. In adopting this method for a class-A amplifier, we obtain over 10% higher efficiency while maintaining the same adjacent channel power ratio (ACPR). The power consumption of additional circuit is 200 µW.

A novel predistortion technique using an automatic average-power bias controlled diode is proposed to compensate the complicated nonlinear characteristics of a microwave class-F power amplifier using an AlGaN/GaN HEMT. The optimum value for diode bias voltage is automatically set according to detected input average RF power level. A high-efficiency 1.9 GHz class-F GaN HEMT power amplifier with the automatic average-power bias control (ABC) diode linearizer achieves an improved third order inter-modulation distortion (IMD3) of better than -45 dBc at a smaller than 6 dB output power back-off from a saturated output power of 27 dBm, without changing drain efficiency. The adjacent channel leakage power ratio (ACPR) for 1.9 GHz W-CDMA signals is below -40 dBc at output power levels of smaller than 20 dBm for the class-F power amplifier.

An analog pre-distortion linearizer employing a radio frequency (RF) transistor with a self base bias control circuit is proposed. The self base bias control circuit extracts the envelope from the modulated input RF signal of the RF transistor and automatically controls its base current according to the extracted envelope. As a result, the proposed linearizer realizes positive gain deviation at high input power level. By adding a resistor between the RF transistor and the self base bias control circuit, the negative gain deviation can be derived. The design of the proposed lineaizer is described with taking the envelope frequency response of the self base bias control circuit into consideration. The fabricated linearizer achieves the adjacent channel power leakage ratio (ACLR) improvement of 8.1 dB for a 2 GHz-band, 10 W-class GaAs FET high-power amplifier (HPA) with negative gain deviation for W-CDMA base stations. It also achieves the ACLR improvement of 8.3 dB for a LDMOS HPA with positive gain deviation for the same application.

A high efficiency SiGe HBT differential power amplifier with an open collector adaptive bias was successfully demonstrated. A novel linearizer consists of an open collector heterojunction bipolar transistor bias circuit and an MOS feedback diode was proposed, which achieved better power added efficiency (PAE) than that of traditional adaptive bias circuits. The size effect of linearizer was investigated and the impedance ratio (R1/R2) between the linearizer and the main amplifier was optimized by the factor of 3. The measured differential power amplifier achieved an output 1-dB compression point (P1 dB) of 18.7 dBm with PAE of 31.2%, the output second order intermodulation point (OIP2) of 59 dBm, and third-order intermodulation point (OIP3) of 28 dBm. Compared to traditional adaptive bias technique, the proposed linearizer power amplifier effectively improved the PAE. The fabricated die size including pads is less than 0.925 mm2 and suitable for highly integrated linear drive amplifier.

We propose a novel adaptive linearization technique for a balanced-amplifier array. The technique uses the specific intermodulation distortions (IMDs) at the output ports in the array. The detected IMD power level can be used to optimize the linearizer's characteristics. Because the design does not need as many power detectors and carrier cancel loops as it does amplifiers, we were able to successfully miniaturize the array-antenna system. This paper describes the principles, verified both experimentally and mathematically for a 4-port amplifier array.

An intermediate frequency (IF) variable gain amplifier (VGA) with exponential gain control for a radio receiver is fabricated in 0.25-µm CMOS technology. The techniques to improve the bandwidth and to reduce temperature dependence of gain are described. The complete VGA is composed of two stages of linearized transconductance VGA and three stages of fixed gain amplifier (FGA). The complete VGA provides a continuous 10 dB to 76.5 dB gain control range, an IIP3 of -11.5 dBm and an NF of 15 dB at 40 MHz.

A moment matrix analysis (MMA) method can derive macroscopic statistical properties such as moments, response time, and power spectra of non-linear equations without solving the equations. MMA expands a non-linear equation into simultaneous linear equations of moments, and reduces it to a linear equation of their coefficient matrix and a moment vector. We can analyze the statistical properties from the eigenvalues and eigenvectors of the coefficient matrix. This paper presents (1) a systematic procedure to linearize non-linear equations and (2) an expansion of the previous work of MMA to derive the statistical properties of various non-linear equations. The statistical properties of the logistic map were evaluated by using MMA and computer simulation, and it is shown that the proposed systematic procedure was effective and that MMA could accurately approximate the statistical properties of the logistic map even though such a map had strong non-linearity.

Moment matrix analysis (MMA) that can derive statistical properties of non-linear equations is presented in this paper. First, non-linear stochastic differential, or difference, equations are approximately expressed by simultaneous linear equations of moments defined at discrete events. Next, by eliminating higher order moments, the simultaneous linear equations are reduced to a linear vector equation of their coefficient matrix and a moment vector comprised of the moments of the system state. By computing the eigenvectors and eigenvalues of the coefficient matrix, we can analyze the moments, transient response, and spectrum of the system state. The behavior of Internet traffic was evaluated by using MMA and computer simulation, and it is shown that MMA is effective for evaluating simultaneous non-linear stochastic differential equations.

This paper proposes a new on-chip linearizer self-adapting to the input power and its implementation to high linear monolithic microwave integrated circuit (MMIC) power amplifier for 1.95 GHz wide-band code division multiple-access (W-CDMA) system. The linearizer consists of InGaP/GaAs heterojunction bipolar transistor (HBT) active bias circuit and reverse biased junction diode of which dynamic admittance to input power level functions adaptively to control the bias to the amplifier. The proposed linearizer has little insertion power loss, and more importantly, it consumes no additional die area and DC power. The HBT MMIC power amplifier with the integrated linearizer exhibits a maximum output power of 30.3 dBm, a power gain of 27.5 dB, a power added efficiency of 42% at the maximum output power under an operation voltage of 3.4 V, and adjacent channel leakage power ratio of -38 dBc at 27 dBm of output power.

In recent years, digital predistortion linearizers have been used in power amplifiers for mobile communications because they are simpler and provide higher power efficiency than conventional feedforward systems. However, in systems that cover a wider frequency band, it is impossible to disregard the frequency characteristics of their various parameters since the degradation that can result causes a decline in output power efficiency which is the most important property of a power amplifier. To date, no detailed studies have been carried out on predistortion compensation systems. Thus, we focused our research on these systems and in this paper we report the simulation and experimental results we obtained for clarifying these effects. In our experiments, we used a W-CDMA power amplifier to determine how much the distortion compensation effect is degraded by the frequency characteristics of analog RF circuits. The results of experiments to determine the relationship between the ACLR (Adjacent Channel Leakage power Ratio) and power efficiency are also reported.

Direct conversion techniques commonly used for the transmitter in basestation rely on analog performance of the quadrature modulator. In this paper, simulated results show that imperfections in analog quadrature modulation--gain and phase error and dc offset--have a devastating effect on digital predistortion for power amplifier linearization circuits. We construct compensation circuit to remove these errors, and conduct an experiment. The imbalance errors are compensated by using the output spectrum of modulator. The image spurious (-56.74 dBm) with gain, phase and the dc offset spurious (-43.83 dBm) are reduced to -93.21 dBm and -93.56 dBm, respectively. These experimental results illustrate that modulation errors can be eliminated.

An 18 GHz-band Microwave Monolithic Integrated Circuit (MMIC) diode linearizer using a parallel capacitor with a bias feed resistance is presented. The newly employed parallel capacitor is able to control gain and phase deviations of the linearizer. This implies that the gain deviation of the linearizer can be controlled without changing the phase deviation. The presented linearizer can compensate the distortion of an amplifier sufficiently. The operation principle of the linearizer with the parallel capacitor is investigated. It is clarified that the gain deviation can be adjusted without changing the phase deviation by using the parallel capacitor. Two variable gain buffer amplifiers and the core part of the linearizer which consists of a diode, a bias feed resistor, and a capacitor are fabricated on the MMIC chip. The amplifiers cancel the frequency dependence of the core part of the linearizer to improve bandwidth of the MMIC. Further, the amplifiers contribute to earn low reflection and compensate insertion loss of the linearizer. The MMIC chip is size of 2.5 mm 1 mm. The linearizer has demonstrated improvement of 3rd Inter-Modulation Distortion (IMD3) of 12 dB at 18 GHz and improvement of more than 6 dB between 17.8 GHz and 18.6 GHz.

In this paper, a predistorter using low frequency intermodulation (IM) signals is proposed. The harmonic generator of the proposed predistorter that consists of a hybrid coupler and four diodes biased separately extracts a second order low frequency IM signal. And with multiplication of second order IM signals, fourth order IM signal is obtained. A vector modulator, modulate fundamental signal with low frequency IM signals, generates predistortion IM signals and controls amplitude/phase of them with modulation factors. As a result, this predistorter is suppressed individual order intermodulation distortion signals of power amplifier effectively. The suggested predistorter has been manufactured to operate in Korea PCS base-station transmitting band (1840-1870 MHz). The test results show that the third order IM is cancelled more than 20 dB and the fifth order IM is cancelled about 10 dB for CW two-tone signals. Also, it's improved the adjacent channel power ratio (ACPR) more than 10 dB for CDMA (IS-95) signals.

An S-band linearizer was developed using GaAs MMIC technology. We call it the even-order-distortion-implemented intermodulation distortion controller (EODIC). EODIC uses even-order intermodulation distortion (IM) components in the second harmonic frequency band to control its IM components in the fundamental frequency band. EODIC is a suitable tool to compensate near-saturated high power amplifiers (HPAs). We developed an EODIC using MMIC technology. This paper describes the principle of EODIC and then introduces the EODIC MMIC in detail. This paper also presents the IM reduction performance of an EODIC in a near-saturated HPA.

We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.

Technologies used to characterize and compensate nonlinearities in microwave power amplifiers are discussed. First, a complex power series representation that allows both amplitude and phase nonlinearities to be dealt with simultaneously is proposed, and in order to estimate the 3rd-order complex coefficient phase of practical amplifiers, two kinds of experimental measurement methods are proposed. Next, the fundamental circuit configuration of IF cuber predistortion linearizer that compensates 3rd-order intermodulation distortion is derived from a nonlinear analysis using complex power series representation. Two practical cuber predistorters for the 6-GHz TWTA and the 800-MHz FET-PA are demonstrated. Moreover, the unique nonlinear compensation technology of side-band inversion is introduced for microwave relay system using TWTAs. Finally, the self-adjusting feed-forward (SAFF)-PA developed for digital cellular base stations is reviewed.

This paper describes amplification with improved linearity by employing a linearizing circuit in an input circuit of an internally-matched Ku-band high power amplifier. The linearizing circuit is composed of series L, C, R and an FET with grounded source and drain, and is connected between the input signal line and ground. This linearizing circuit was applied to a Ku-band 10 W output power amplifier utilizing a 25.2 mm gate-width double-doped Heterojunction FET. The power amplifier demonstrated a 8 dB reduction of the third-order intermodulation at about 6 dB output power backoff point from the 2 dB output compression point.

In many efforts to increase the efficiency of power amplifiers of mobile terminals, compensation of nonlinear distortion based on an adaptive predistortion method has performed an important role. In the course of basic evaluation of a method using a look-up table (LUT) and a method using an approximation for compensation of nonlinear distortion, a newly developed method using approximation and a ROM type LUT with a small-sized memory has been proposed to overcome barriers to practical application and disadvantages associated with the LUT method. Experimental trials of the proposed method were applied to narrow-band digital modulation systems. As a result, the proposed method was found to provide a satisfactory capability of compensating nonlinear distortion, with next adjacent channel interference of less than -55 dBc. The proposed method has advantages such as a small memory size and excellent RF performance, and is expected to occupy an important position in many adaptive predistortion methods.

This paper describes the design, fabrication, and performance of a GaAs FET linearizer with a large source inductance, focusing mainly on (a) a mechanism of positive gain and negative phase deviations for input power, (b) stability considerations, and (c) a dependence on load impedance. In addition, in an application to the linearized amplifier, it is shown that an improvement can be achieved for adjacent channel leakage power (ACP) and third order intermodulation distortion (IM3) with the use of the linearizer.