Due to a rather low phoneme recognition rate for noisy telephone speech, there may arise large differences between N-gram built upon recognized phoneme labels and those built upon original attached phoneme labels, which in turn would affect the performances of N-gram based language identification methods. Use of N-gram built upon recognized phoneme labels from the training data was evaluated and was shown to be more effective for the language identification. The performance of mixed phoneme recognizer, in which both language-dependent and language-independent phonemes were included, was also evaluated. Results showed that the performance was better than that using parallel language-dependent phoneme recognizers in which bias existed due to different numbers of phonemes among languages.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

We propose an approach to obtain the relation between the number of voice call users and the number of data call users in the reverse link of a DS-CDMA cellular system with mixed rate traffic. The analyzed results show that as the number of data call users with high bit rate increases, the number of allowable voice call users decreases rapidly and linearly.

The following, which is related to the design of the microwave filters, is mainly presented: (1) certain useful approximation which can be obtained by double-resistive- terminated 2-ports consisting of a cascade of two 1-variable 2-ports in different variables, and (2) an approach for filter design from 2-variable viewpoint. Approximations presented provide useful magnitude responses in 2-D domain. Hence it is discussed that how the provided 2-D responses can be used for the design of the microwave filters. Furthermore, properties of the 2-variable transfer functions resulting in such circuits are given.

Mixed Quasi Newton simulation algorithm that is capable of calculating analog circuits containing mixed level of element models is presented. Conventional circuit simulators usually apply Newton method to solve nonlinear system equations resulted from circuit equations. At each Newton iteration step, it is necessary to reevaluate the Jacobian stamp of circuit elements. However, obtaining the Jacobian stamp of elements described by complex behavior models is a computationally expensive process. To reduce the number of Jacobian evaluations, we combine Newton method and Quasi-Newton method as a new updating scheme. The simulation results show that our algorithm can reduce the number of Jacobian evaluations and improve the simulation time, particularly when simulating circuits containing many behavior model elements.

Electroluminescent (EL) devices with mixed single layer that consist of fluorescent dyes, distylylbiphenyl derivative (DPVBi) and triphenylamine derivative (TPD), are studied. Blue light emission was observed from the device with DPVBi and TPD. White emission over 2,500 cd/m2 was observed from the devices with mixed single layer of DPVBi, TPD and dicyanomethylene derivative (DCM).

A method called "active guard band filtering" is proposed for reducing substrate noise in analog and digital mixed-signal integrated circuits. A noise cancellation signal having an inverse value to the substrate noise is actively input into a guard band to suppress the substrate noise. An operational amplifier produces the noise cancellation signal based upon the substrate noise detected by one guard band and feeds this signal through another quard band into the substrate. This is done within the amplifier feedback loop, which includes the guard bands and the substrate. The noise suppression effect was measured by using 0.8µm CMOS test chip. Using active guard band filtering suppressed substrate noise to -40 dB of the original non-canceled noise level at 8 MHz. The noise suppression effect was also observed at frequencies up to 20MHz, with an external operational amplifier. The influence of parasitic impedance was found to be a key factor in noise suppression. An active guard band filter with an on-chip noise cancellation circuit will be even more effective for high frequencies, because it eliminates parasitic impedance due to external components.

Digital-switching noise coupled into sensitive analog circuits is a critical problem in large-scale integration of mixed analog and digital circuits. This paper describes noise coupling of this kind, especially, through the substrate in CMOS integrated circuits, and reviews recent technical solutions to this noise problem. Simplified models have been developed to simulate the substrate coupling rapidly and accurately. A method using a CMOS comparator was proposed for measuring the effects of substrate noise, and equivalent waveforms of actual substrate noise were obtained. A circuit tecnique, called active guard band filtering, that controls the noise source is a new approach to substrate noise decoupling. CAD methods for handling substrate-coupled switching noise are making design verification possible for practical mixed-signal LSIs.

A structural active-object system (SAOS) is a transition-based object-oriented system suitable for rapid development of hardware logic simulators. A SAOS consists of a collection of interacting structural active objects (SAOs), whose behaviors are determined by the transition statements provided in their class definitions. Furthermore, SAOs can be structurally and hierarchically composed from their component SAOs like hardware components. These features allow SAOs to model components for circuit simulation more naturally than passive objects used in ordinary object-oriented programming. Also, we can easily create new kinds of components by using the inheritance mechanism. Executions of transition statements may be event-and/or time-driven, and hence digital, analog, and mixed-mode simulation is possible. Prototype simulation programs with graphical user interfaces have been developed as SAOS programs for digital, analog, and mixed-mode circuit simulation.

Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. This paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving this problem is constructed as an extension of conventional pitchmatching algorithms. The computational complexity is also discussed in comparison with a conventional naive algorithm. Finally, examples and application results to realistic layouts are presented.

Ba ferrite films were deposited epitaxially on ZnO underlayer from targets with composition of BaO-6.5Fe2O3 at substrate temperature of 600 using the facing targets sputtering apparatus. The gas mixture of Ar and Xe of 0.18 Pa and O2 of 0.02 Pa was used as the sputtering gas and the dependences of crystallographic and magnetic characteristics on the partial Xe pressure PXe(0.0-0.18 Pa) were investigated. Films deposited at various PXe were composed of BaM ferrite and spinel crystallites, and the minimum centerline average roughness Ra of 8.3 nm was obtained at PXe of 0.10 Pa. Since saturation 4πMs of 5.1 kG and perpendicular anisotropy constant Ku1 of 4.23105 Jm-3 were larger than those of bulk BaM ferrite of 4.8 kG and 3.30105 Jm-3, respectively, these films appeared promising for use as perpendicular recording media.

This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

This paper focuses on Mixed Reality (MR) visual displays, a particular subset of Virtual Reality (VR) related technologies that involve the merging of real and virtual worlds somewhere along the virtuality continuum" which connects completely real environments to completely virtual ones. Probably the best known of these is Augmented Reality (AR), which refers to all cases in which the display of an otherwise real environment is augmented by means of virtual (computer graphic) objects. The converse case on the virtuality continuum is therefore Augmented Virtuality (AV). Six classes of hybrid MR display environments are identified. However, an attempt to distinguish these classes on the basis of whether they are primarily video or computer graphics based, whether the real world is viewed directly or via some electronic display medium, whether the viewer is intended to feel part of the world or on the outside looking in, and whether or not the scale of the display is intended to map orthoscopically onto the real world leads to quite different groupings among the six identified classes, thereby demonstrating the need for an efficient taxonomy, or classification framework, according to which essential differences can be identified. The obvious' distinction between the terms real" and virtual" is shown to have a number of different aspects, depending on whether one is dealing with real or virtual objects, real or virtual images, and direct or non-direct viewing of these. An (approximately) three dimensional taxonomy is proposed, comprising the following dimensions: Extent of World Knowledge (how much do we know about the world being displayed?"), Reproduction Fidelity (how realistically' are we able to display it?"), and Extent of Presence Metaphor (what is the extent of the illusion that the observer is present within that world?").

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

This paper presents a mathematical formulation of a data path allocation and floorplanning problem using the mixed integer linear programming, and shows some experimental results. We assume that a data flow graph and the scheduled result are given in advance. The chip area and total wire length are used for the quality measures of the solution for the problem. This method is applied to some examples, and compared with the other method reported previously in the points of the solution and computation time.

For the efficient circuit simulation, several direct/relaxation-based mixed mode simulation techniques have been studied. This paper proposes the combination of selective trace, which is well-known in the logic simulation, with dynamic network separation. In the selective trace method, the time points to be analyzed are selected for each subcircuit. Since the separation technique enables the analysis of each subcircuit independently, it is possible to skip solving the latent subcircuits, according to selective trace. Selecting the time points in accordance with activity of each subcircuit is analogous to multirate numerical integration technique used in the waveform relaxation algorithm.

This paper describes mixed gas systems of SO2 and NO2 which are the essential corrosive gases in an ordinary atmospheric environment of electronic parts. It describes the corrosion product compositions and the behavior of copper in mixed and separate gases. Results of our tests show the following: (1) The weight of corrosion products with the SO2-NO2 mixed gas approximate the sum of those with the individual gases, however, the corrosion products of SO2 are affected by NO2. (2) Tests of the SO2-NO2 mixed gas closely simulates tests of electronic parts in the ordinary atmospheric environment.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.