This paper presents a technique to reduce the quantum cost by making temporary changes to the functionality of a given Boolean function. This technique is one of the very few known methods based on manipulating Exclusive-or Sum-Of-Products (ESOP) expressions to reduce the quantum cost of the corresponding circuit. The idea involves adding Mixed Polarity Multiple-Control Toffoli (MPMCT) gates to temporarily change the functionality of the given function, so that the modified function has a smaller quantum cost. To compensate for the temporary change, additional gates are inserted into the circuit. The proposed method finds a small ESOP expression for the given function, and then finds a good pair of product terms in the ESOP expression so that the quantum cost can be reduced by applying the transformation. The proposed approach is likely to produce a better quantum cost reduction than the existing methods, and indeed experimental results confirm this expectation.

The rapid prototyping of a mixed-signal system-on-chip (SoC) has been enabled by reusing predesigned intellectual properties (IPs) and by integrating newly designed IP into the top design of SoC. The IPs have been designed on various hardware description levels, which leads to challenges in simulations that evaluate the prototyping. One traditional solution is to convert these heterogeneous IP models into equivalent models, that are described in a single description language. This conversion approach often requires manual rewriting of existing IPs, and this results in description loss during the model projection due to the absence of automatic conversion tools. The other solutions are co-simulation/emulation approaches that are based on the coupling of multiple simulators/emulators through connection modules. The conventional methods do not have formal theoretical backgrounds and an explicit interface for integrating the simulator into their solutions. In this paper, we propose a general co-simulation approach based on the high-level architecture (HLA) and a newly-defined programming language interface for interoperation (PLI-I) between heterogeneous IPs as a formal simulator interface. Based on the proposed PLI-I and HLA, we introduce formal procedures of integration and interoperation. To reduce integration costs, we split these procedures into two parts: a reusable common library and an additional model-dependent signal-to-event (SE) converter to handle differently abstracted in/out signals between the coupled IPs. During the interoperation, to resolve the different time-advance mechanisms and increase computation concurrency between digital and analog simulators, the proposed co-simulation approach performs an advanced HLA-based synchronization using the pre-simulation concepts. The case study shows the validation of interoperation behaviors between the heterogeneous IPs in mixed-signal SoC design, the reduced design effort in integrating, and the synchronization speedup using the proposed approach.

This report presents experimental measurements of mixed-mode oscillations (MMOs) generated by a weakly driven four-segment piecewise linear Bonhoeffer-van der Pol (BVP) oscillator. Such a roughly approximated simple piecewise linear circuit can generate MMOs and mixed-mode oscillation-incrementing bifurcations (MMOIBs). The laboratory experiments well agree with numerical results. We experimentally and numerically observe time series and Lorenz plots of MMOs generated by successive and nonsuccessive MMOIBs.

This letter presents a method for solving several linear equations in max-plus algebra. The essential part of these equations is reduced to constraint satisfaction problems compatible with mixed integer programming. This method is flexible, compared with optimization methods, and suitable for scheduling of certain discrete event systems.

The orthogonal array is an important object in combinatorial design theory, and it is applied to many fields, such as computer science, coding theory and cryptography etc. This paper mainly studies the existence of the mixed orthogonal arrays of strength two with seven factors and presents some new constructions. Consequently, a few new mixed orthogonal arrays are obtained.

In this paper, optimal control of multi-vehicle systems is studied. In the case where collision avoidance between vehicles and obstacle avoidance are imposed, state discretization is effective as one of the simplified approaches. Furthermore, using state discretization, cooperative actions such as rendezvous can be easily specified by linear temporal logic (LTL) formulas. However, it is not necessary to discretize all states, and partial states (e.g., the position of vehicles) should be discretized. From this viewpoint, a new control method for multi-vehicle systems is proposed in this paper. First, the system in which partial states are discretized is formulated. Next, the optimal control problem with constraints described by LTL formulas is formulated, and its solution method is proposed. Finally, numerical simulations are presented. The proposed method provides us a useful method in control of multi-vehicle systems.

Counting the number of differentially active S-boxes is of great importance in evaluating the security of a block cipher against differential attack. Mouha et al. proposed a technique based on Mixed-Integer Linear Programming (MILP) to automatically calculate a lower bound of the number of differentially active S-boxes for word-oriented block ciphers, and applied it to symmetric ciphers AES and Enocoro-128v2. Later Sun et al. extended the method by introducing bit-level representations for S-boxes and new constraints in the MILP problem, and applied the extended method to PRESENT-80 and LBlock. This kind of methods greatly depends on the constraints in the MILP problem describing the differential propagation of the block cipher. A more accurate description of the differential propagation leads to a tighter bound on the number of differentially active S-boxes. In this paper, we refine the constraints in the MILP problem describing XOR operations, and apply the refined MILP modeling to determine a lower bound of the number of active S-boxes for the Lai-Massey type block cipher FOX in the model of single-key differential attack, and obtain a tighter bound in FOX64 than existing results. Experimental results show that 6, instead of currently known 8, rounds of FOX64 is strong enough to resist against basic single-key differential attack since the differential characteristic probability is upper bounded by 2-64, and thus the maximum differential characteristic probability of 12-round FOX64 is upper bounded by 2-128, where 128 is the key-length of FOX64. We also get the lower bound of the number of differentially active S-boxes for 5-round FOX128, and proved the security of the full-round FOX128 with respect to single-key differential attack.

This study proposes a novel method for evaluating the transmission characteristics of a three-phase filter using the “Fortescue-mode S-parameters,” which are S-parameters whose variables are transformed into symmetrical coordinates (i.e., zero-/positive-/negative-phase sequences). The behavior of the filter under three-phase current, including its non-symmetry, can be represented by these S-parameters, without regard to frequency. This paper also describes a methodology for creating modal equivalent circuits that reflect Fortescue-mode S-parameters allowing the effects of circuit components on filter characteristics to be estimated. Thus, this method is useful not only for the measurement and evaluation but also for the analysis and design of a three-phase filter. In addition, the physical interpretation of asymmetrical/symmetrical insertion losses and the conversion method based on Fortescue-mode S-parameters are clarified.

A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced~(HCI) degradation is presented. The supply voltage of the last stage of the PA ($V_{{ m PA}}$) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21,mm$^{2}$, which provides a saturation power of 10.1,dBm to 13.2,dBm with a peak power-added efficiency~(PAE) of 8.1% to 15.0% for the supply voltage $V_{{ m PA}}$ which varies from 0.7,V to 1.0,V at 60,GHz, respectively.

This paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL transistor is one future device which enables 3D IC and chip shrinking technology.

Many kinds of data can be represented as a network or graph. It is crucial to infer the latent structure underlying such a network and to predict unobserved links in the network. Mixed Membership Stochastic Blockmodel (MMSB) is a promising model for network data. Latent variables and unknown parameters in MMSB have been estimated through Bayesian inference with the entire network; however, it is important to estimate them online for evolving networks. In this paper, we first develop online inference methods for MMSB through sequential Monte Carlo methods, also known as particle filters. We then extend them for time-evolving networks, taking into account the temporal dependency of the network structure. We demonstrate through experiments that the time-dependent particle filter outperformed several baselines in terms of prediction performance in an online condition.

Many controllers are implemented on digital platforms as periodic control tasks. But, in embedded systems, an amount of resources are limited and the reduction of resource utilization of the control task is an important issue. Recently, much attention has been paid to a self-triggered controller, which updates control inputs aperiodically. A control task by which the self-triggered controller is implemented skips the release of jobs if the degradation of control performances by the skipping can be allowed. Each job computes not only the updated control inputs but also the next update instant and the control task is in the sleep state until the instant. Thus the resource utilization is reduced. In this paper, we consider self-triggered predictive control (stPC) of mixed logical dynamical (MLD) systems. We introduce a binary variable which determines whether the control inputs are updated or not. Then, we formulate an stPC problem of mixed logical dynamical systems, where activation costs are time-dependent to represent the preference of activations of the control task. Both the control inputs and the next update instant are computed by solving a mixed integer programming problem. The proposed stPC can reduce the number of updates with guaranteeing stability of the controlled system.

This paper proposes a robust bilateral filter which can handle mixed Gaussian and impulsive noise by hybridizing the conventional bilateral filter and the switching median filter. The effectiveness of the proposed method is verified in comparison with other conventional methods by some experiments using the natural digital images.

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design.

Large-scale introduction of renewable energy such as photovoltaic energy and wind is a big motivation for renovating conventional grid systems. To be independent from existing power grids and to use renewable energy as much as possible, a decentralized energy network is proposed as a new grid system. The decentralized energy network is placed among houses to connect them with each other, and each house has a PV panel and a battery. A contribution of this paper is a network topology and battery size exploration for the decentralized energy network in order to make effective use of renewable energy. The proposed method for exploring the decentralized energy network design is inspired by the design methodology of VLSI systems, especially design space exploration in system-level design. The proposed method is based on mixed integer programming (MIP) base power flow optimization, and it was evaluated for all design instances. Experimental results show that the decentralized energy network has the following features. 1) The energy loss and energy purchased due to power shortage were not affected by each battery size but largely affected by the sum of all battery sizes in the network, and 2) the network topology did not largely affect the energy loss and the purchased energy. These results will become a useful guide to designing an optimal decentralized energy network for each region.

The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

Substrate coupling of radio frequency (RF) components is represented by equivalent circuits unifying a resistive mesh network with lumped capacitors in connection with the backside of device models. Two-port S-parameter test structures are used to characterize the strength of substrate coupling of resistors, capacitors, inductors, and MOSFETs in a 65 nm CMOS technology with different geometries and dimensions. The consistency is finely demonstrated between simulation with the equivalent circuits and measurements of the test structures, with the deviation of typically less than 3 dB for passive and 6 dB for active components, in the transmission properties for the frequency range of interest up to 8 GHz.

The recent increase in mobile data traffic has resulted in service quality problems. Although an economic approach to control congestion can be achieved by pricing, the current pricing schedule of mobile data services instead causes smartphone users to create more traffic. We establish a pricing model based on the distribution of demand types among heterogeneous users to improve the current tariff structure; our method mixes usage-based and fixed-fee pricing schemes. The results derived from the application of this model to survey data on willingness-to-pay for mobile data service demonstrate that the provider can decrease the amount of data traffic and increase the expected revenue by lowering the price for a unit of data and raising the fixed-fee level for unlimited service. The model also explains the changing weight of usage-based and fixed-fee pricing schemes by considering shifts in the type distribution through service evolution and proposes pricing strategies for future communications services.

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18 µm technology, the core area of the processor is 3.47 mm2 and the maximum operating frequency can be up to 500 MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

We have proposed a novel call admission control (CAC) for maximizing total user satisfaction in a heterogeneous traffic network and showed the effectiveness of our CAC by using an optimal threshold from numerical analysis [1]. In our previous CAC, when a new broadband flow arrives and the total accommodated bandwidth is more than or equal to the threshold, the arriving new broadband flow is rejected. In actual networks, however, users may agree to wait for a certain period until the broadband flow, such as video, begins to play. In this paper, when total accommodated bandwidth is more than or equal to the threshold, arriving broadband flows wait instead of being rejected. As a result, we can greatly improve total user satisfaction.