A 19.1-to-20.4 GHz sigma-delta fractional-N frequency synthesizer with two-point modulation (TPM) for frequency modulated continuous wave (FMCW) radar applications is presented. The FMCW synthesizer proposes a digital and voltage controlled oscillator (D/VCO) with large continuous frequency tuning range and small digital controlled oscillator (DCO) gain variation to support TPM. By using TPM technique, it avoids the correlation between loop bandwidth and chirp slope, which is beneficial to fast chirp, phase noise and linearity. The start frequency, bandwidth and slope of the FMCW signal are all reconfigurable independently. The FMCW synthesizer achieves a measured phase noise of -93.32 dBc/Hz at 1MHz offset from a 19.25 GHz carrier and less than 10 µs locking time. The root-mean-square (RMS) frequency error is only 112 kHz with 94 kHz/µs chirp slope, and 761 kHz with a fast slope of 9.725 MHz/µs respectively. Implemented in 65 nm CMOS process, the synthesizer consumes 74.3 mW with output buffer.

Phase locking with frequency tuning is demonstrated for a resonant-tunneling-diode terahertz oscillator integrated with a biased varactor diode. The tuning range of oscillation frequency is 606-613GHz. The phase noise in the output of the oscillator is transformed to amplitude noise, and fed back to the varactor diode together with bias voltage. The spectral linewidth at least <2Hz was obtained at the oscillation frequencies tuned by the bias voltage of the varactor diode.

We developed a 5.8 GHz power-variable phase-controlled magnetron (PVPCM) which controls the phase of magnetron output by a phase shifter and controls the power by the anode current of the magnetron. This method is different from the previous 2.45 GHz phase-controlled magnetron which utilizes an injection method and a phase locked loop by the anode current, since the frequency of 5.8 GHz magnetron hardly changes with the anode current. Our experiments show that the developed 5.8 GHz PVPCM had a variable output power with 1% power stability from 160 W to 329 W, the phase accuracy was nearly ±1°, and the response time was less than 100 µs. Stable output power, high phase-controlled accuracy, and fast response speed microwave sources based on the PVPCMs are suitable for phased array system for wireless power transfer.

To provide a satellite communication system with high reliability for social infrastructure, building flexible beam adapting to change of communication traffic is necessary. Optical Beam Forming Network has the capability of broadband transmission and small light construction. However, in space environment, there are concerns that the reception efficiency is reduced by the relative phase error of receiving signal among antenna elements with temperature fluctuation. To prevent this, we control relative phase among received signals with optical phase locked loop. In this paper, we propose the active optical phased array system using multi dither heterodyning technique for receiving OBF, and present experimental results under temperature fluctuation. We evaluated the stability of relative phase among 3 elements for temperature fluctuation at multiplexer from -15 to 45, and checked the stability of PLL among 3 elements.

High gain extinction ratio and stable control of the phase in phase sensitive amplification are fundamental to realize either phase regeneration or quadrature squeezing of phase modulated signals in an efficient and robust manner. In this paper, we show that a combination of our previously demonstrated “sideband-assisted” dual-pump phase sensitive amplifier with a gain extinction ratio of more than 25dB, and a phase-locked loop based stabilization technique, enable efficient QPSK quadrature squeezing. Its stable operation is exploited to realize phase de-multiplexing of QPSK signals into BPSK tributaries. The phase de-multiplexed signals are evaluated through measurement of constellation diagrams, eye diagrams and more importantly, BER curves. The de-multiplexed BPSK signals exhibited an OSNR penalty of less than 1dB compared to the back-to-back BPSK signals.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

In this letter, an improved triple-tunable frequency synthesizer structure to achieve both high frequency resolution and fast switching speed without degradation of spurious signals (spurs) level performance is proposed. According to this structure, a high performance millimeter-wave frequency synthesizer with low spurious, low phase noise, and fast switching speed, is developed. This synthesizer driven by the direct digital synthesizer (DDS) AD9956 can adjust the output of a DDS and frequency division ratios of two variable frequency dividers (VFDs) to move the spurious components outside the loop bandwidth of the phase-locked loop (PLL). Moreover, the ADF4252 based microwave PLL can further suppress the phase noise. Experimental results from the implemented synthesizer show that remarkable performance improvements have been achieved.

The LC-based Digitally Controlled Oscillator (DCO) is one of the most important components of all digital phase locked loops. The performance of the loops is significantly determined by the DCO's frequency resolution. In order to enhance the frequency resolution, we propose a mismatched capacitor pairs based digitally controlled switched capacitance array, which dramatically reduces the minimum switched varactor capacitance. Furthermore, we implement a DCO based on our proposal in SMIC 0.18 µm and conduct simulation in Spectre. The simulation results show that the frequency resolution is enhanced compared with the existing methods.

This paper presents an automatic adjustment of the transfer function of phase locked loop (PLL). The time constants and the gain factor of the transfer function are adjusted without opening the loop of PLL. The time constant adjustment is performed using a replica of the 1st order RC low pass filter and the gain factor is adjusted by detecting the open loop gain at the unity gain frequency. These adjustments are automatically carried out using a digitally controlled capacitance array and a digitally controlled charge pump. The proposed calibration can reduce the bandwidth error of 30% to 5% and the gain error of 7 dB to 1 dB.

Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.

It is an innovative idea for modern PLL generation to control the bandwidth proportionally to the reference frequency. Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. A new compact switched capacitor (SC) filter which has fully flat response has been developed for adaptive biased PLLs. We have also developed a new digital control method for achieving the wider frequency range. The measured performances of the test chip were good enough for the use in the microprocessors.

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-µm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.

An 8-GS/s 4-bit CMOS analog-to-digital converter (ADC) chip was implemented by using a time interleaved flash architecture for very high frequency mixed signal applications with a 0.18-µm single-poly five-metal CMOS process. Eight 1-GS/s flash ADCs were time-interleaved to achieve the 8-GHz sampling rate. Eight uniformly-spaced 1 GHz clocks were generated by using a phase-locked-loop (PLL) with the peak-to-peak and rms jitters of 29.6 ps and 3.78 ps respectively. An input buffer including a preamplifier array (fifteen preamplifiers, four dummy amplifiers and averaging resistors) was shared among eight 1-GS/s flash ADCs to reduce the input capacitance and the mismatches among eight 1-GS/s flash ADCs. The adjacent output nodes of preamplifiers were connected by a resistor (resistor-averaging) to reduce the effects of the input offset voltage and the load mismatches of preamplifiers. A source follower circuit was added at the output node of a preamplifier to drive eight distributed track and hold (DTH) circuits. The Input bandwidth of ADC was measured to be 2.5 GHz. The measured SFDR values at the sampling rate of 8-GS/s were 25 dB and 22 dB for the 1.033 GHz and 2.5 GHz sinusoidal input signals respectively. The power consumption and the active input voltage range were 340 mW and 700 mV peak-to-peak, respectively, at the sampling rate of 8-GS/s and the supply voltage of 1.8 V. The active chip area was 1.32 mm2.

A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25 µm fabrication process and its performance is verified by measurement results.

This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

Recent advances make it possible to mitigate a number of drawbacks of conventional phase locked loops. These advances permit the design of phase tracking system with much improved characteristics that are sought after in modern communication system applications. A new phase tracking system is outlined which reduces the effects of VCO phase noise to an insignificant level. This fact permits extremely narrow bandwidth phase tracking systems to be realized, even when a VCO with poor phase noise characteristics is employed. The improvement in performance over conventional phase locked loops is analyzed. The new phase tracking system also has other benefits such as precise centre frequency and elimination of peaking in the transfer function. To implement the phase tracking system requires a frequency measurement. We outline a new highly integrated frequency measurement method suitable for narrow bandwidth applications. Experimental results from a prototype confirms theoretical results.

We consider a network consisting of phase locked loops coupled one another through frequency dividers. When the network structure is rotationally symmetric, spatially periodic simple patterns in terms of the phase of the PLLs are formed. The patterns determine the lock-in frequency of the network. The stability of the pattern is determined by the spatially distributed simple coupling weight patterns. Therefore, a signal with which the network synchronizes is indirectly selected by the weight patterns when several signals are simultaneously applied to the network. The selectivity plays an important role in an intelligent network model.

In this paper, we subjects the case that frequency–shift–keying (FSK) modulation and phase locked loop (PLL) demodulator are used in frequency hopped spread spectrum (FH–SS) communication system. So the carrier frequencies of undesired transmitters may come into collision with the carrier frequency of desired transmitter in this communication system, we evaluate the response of PLL by two sinusoidal inputs so as to estimate how the response of PLL demodulator is affected by the collision of carrier frequencies. First, we compute the synchronization diagrams of PLL with two sinusoids. From this, it is indicated that allowable value of amplitude ratio of interference transmitter's signal to disired transmitter's signal decreases with increasing FSK modulation width of desired transmitter. Next, we calculated the output of PLL demodulator with two sinusoids. To this end, it is shown that the allowable value of amplitude ratio is bounded by a constant value even if FSK modulation width is enough small.