This paper presents analysis and design of passive RC polyphase filters (RCPFs) in tutorial style. Single-phase model of a single-stage RCPF is derived, and then, multi-stage RCPFs are analyzed and obtained some restrictions for realizable poles and zeros locations of RCPFs. Exact design methods of RCPFs with equal ripple type, and Butterworth type responses are explained for transfer function design and element value design along with some design examples.

Quasi-phase-matching (QPM) electro-optic modulators using gap-embedded patch-antennas were proposed for improving wireless microwave-optical signal conversion. The proposed QPM devices can receive wireless microwave signals and convert them to optical signals directly. The QPM structures enable us to have twice antenna elements in the fixed device length. The device operations with improved conversion efficiency of 10 dB were experimentally demonstrated at a wireless signal frequency of 26 GHz. The proposed QPM devices were also tested to a wireless-over-fiber link.

High phase noise is a common problem in ring oscillators. Continuous conduction of the transistor in an analog tuning method degrades the phase noise of ring oscillators. In this paper, a digital control tuning which completely switches the transistors on and off, and a 1/f noise reduction technique are employed to reduce the phase noise. A 14-bit control signal is employed to obtain a small frequency step and a wide tuning range. Furthermore, multiphase ring oscillator with a sub-feedback loop topology is used to obtain a stable quadrature outputs with even number of stages and to increase the output frequency. The measured DCO has a frequency tuning range from 554 MHz to 2.405 GHz. The power dissipation is 112 mW from 1.8 V power supply. The phase noise at 4 MHz offset and 2.4 GHz center frequency is -134.82 dBc/Hz. The FoM is -169.9 dBc/Hz which is a 6.3 dB improvement over the previous oscillator design.

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.

In this paper, using the Linear Time Variant (LTV) phase noise model and considering higher order harmonics generated by the oscillator output signal, a more general formula for transformation of the excess phase to the output signal is presented. Despite the basic LTV model which assumes that the total carrier power is within the fundamental harmonic, in the proposed model, the total carrier power is assumed to be distributed among all output harmonics. For the first harmonic, the developed expressions reduce to the basic LTV formulas. Simulation and experimental results are used to ensure the validity of the model.

This paper presents two halftoning methods to improve efficiency in generating structurally similar halftone images using Structure Similarity Index Measurement (SSIM). Proposed Method I reduces the pixel evaluation area by applying pixel-swapping algorithm within inter-correlated blocks followed by phase block-shifting. The effect of various initial pixel arrangements is also investigated. Proposed Method II further improves efficiency by applying bit-climbing algorithm within inter-correlated blocks of the image. Simulation results show that proposed Method I improves efficiency as well as image quality by using an appropriate initial pixel arrangement. Proposed Method II reaches a better image quality with fewer evaluations than pixel-swapping algorithm used in Method I and the conventional structure aware halftone methods.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

This paper proposes an easy-to-design, theory-consistent compact feeding circuit, with a single input and four outputs, being comprised of two hybrid circuits that are capable of switching a beam in three directions. The circuits that determine the phase differences between the antennas are present on the same single layer, and thus there is no effect of vias and the design agrees well with the underlying theory. In addition, the vertically and horizontally symmetrical circuit pattern contributes to a substantial reduction in design time. The circuit is designed for use in the ISM band and its properties are evaluated using an RF circuit simulator. A prototype is fabricated and evaluated. The results of the simulation and measurement agree well with the theoretical values. The dimensions of the feeding circuit are 75 (H)55 (W)3.0 (T) mm.

We propose a methodology of loop design optimization for fourth-order fractional-N phase locked loop (PLL) frequency synthesizers featuring a short settling time of 5 µsec for applications in an active RFID (radio frequency identification) and automobile smart-key systems. To establish the optimized design flow, equations presenting the relationship between the specification and PLL loop parameters in terms of settling time, loop bandwidth, phase margin, and phase noise are summarized. The proposed design flow overcomes the settling time inaccuracy in conventional second-order approximation methods by obtaining the accurate relationship between settling time and loop bandwidth with the MATLAB Control System Toolbox for the fourth-order PLLs. The proposed flow also features the worst-case design by taking account of the process, voltage, and temperature (PVT) variations in loop filter components, and considers the tradeoff between phase noise and area. The three-step optimization process consists of 1) the derivation of the accurate relationship between the settling time and loop bandwidth for various PVT conditions, 2) the derivation of phase noise and area as functions of area-dominant filter capacitance, and 3) the derivation of all PLL loop components values. The optimized design result is compared with circuit simulations using an actually designed fourth-order fractional-N PLL in a 1.8 V 0.18 µm CMOS technology. The error between the design and simulation for the setting time is reduced from 0.63 µsec in the second-order approximation to 0.23 µsec in the fourth-order optimization that proves the validity of the proposed method for the high-speed settling operations.

This letter investigates an iterative learning control with advanced output data (ADILC) scheme for non-minimum phase (NMP) systems when the number of NMP zeros is unknown. ADILC has a simple learning structure that can be applied to both minimum phase and NMP systems. However, in the latter case, it is assumed that the number of NMP zeros is already known. In this paper, we propose an ADILC scheme in which the number of NMP zeros is unknown. Based on input-to-output mapping, the learning starts from the relative degree. When the input becomes larger than a certain upper bound, we redesign the input update law which consists of the relative degree and the estimated value for the number of NMP zeros.

This paper proposes a comb filter design method which utilizes two linear phase FIR filters for flexibly adjusting the comb filter's frequency response. The first FIR filter is used to individually adjust the notch gains, which denote the local minimum gains of the comb filter's frequency response. The second FIR filter is used to design the elimination bandwidths for individual notch gains. We also derive an efficient comb filter by incorporating these two FIR filters with an all-pass filter which is used in a conventional comb filter to accurately align the nulls with the undesired harmonic frequencies. Several design examples of the derived comb filter show the effectiveness of the proposed comb filter design method.

In this paper, we propose a method capable of shortening the distance from a noise detection microphone to a loudspeaker in active noise control system with non-minimum phase secondary path. The distance can be basically shortened by forming the noise control filter, which produces the secondary noise provided by the loudspeaker, with the cascade connection of a non-recursive filter and a recursive filter. The output of the recursive filter, however, diverges even when the secondary path includes only a minimum phase component. In this paper, we prevent the divergence by utilizing MINT (multi-input/output inverse theorem) method increasing the number of secondary paths than that of primary paths. MINT method, however, requires a large scale inverse matrix operation, which increases the processing cost. We hence propose a method reducing the processing cost. Actually, MINT method has only to be applied to the non-minimum phase components of the secondary paths. We hence extract the non-minimum phase components and then apply MINT method only to those. The order of the inverse matrix thereby decreases and the processing cost can be reduced. We finally show a simulation result demonstrating that the proposed method successfully works.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

We have demonstrated switching characteristics in a wavelength switch based on multiple GaInAs/InP quantum wells. It consisted of straight arrayed waveguides with a linearly varying refractive index distribution. The refractive index can be changed via the thermo-optic (TO) effect. Using a Ti/Au thin-film heater to generate the TO effect, we realized four-port switching at four demultiplexed wavelengths. In addition, by changing the structure of the heater from rectangular to triangular, the power consumption for four-port switching was reduced by half.

This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.

Shape is one of the primary low-level image features in content-based image retrieval. In this paper we propose a new shape description method that consists of a rotationally invariant angular radial transform descriptor (IARTD). The IARTD is a feature vector that combines the magnitude and aligned phases of the angular radial transform (ART) coefficients. A phase correction scheme is employed to produce the aligned phase so that the IARTD is invariant to rotation. The distance between two IARTDs is defined by combining differences in the magnitudes and aligned phases. In an experiment using the MPEG-7 shape dataset, the proposed method outperforms existing methods; the average BEP of the proposed method is 57.69%, while the average BEPs of the invariant Zernike moments descriptor and the traditional ART are 41.64% and 36.51%, respectively.

This paper investigates the non-data-aided (NDA) carrier frequency estimation of amplitude and phase shift keying (APSK) signals. The true Cramer-Rao bound (CRB) for NDA frequency estimation of APSK signals are derived and evaluated numerically. Characteristic and jitter variance of NDA Luise and Reggiannini (L&R) frequency estimator are analyzed. Verified by Monte Carlo simulations, the analytical results are shown to be accurate for medium-to-high signal-to-noise ratio (SNR) values. Using the proposed closed-form expression, parameters of the algorithm are optimized efficiently to minimize the jitter variance.

The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4 V, the maximum operating speed changes by about 40–50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

An amplitude-redistribution technique – which improves phase-noise performance of millimeter (mm)-wave and quasi mm-wave cross-coupled VCOs by controlling the distribution of voltage swings on the oscillator nodes – is proposed. A 28-GHz VCO, fabricated in 0.13-µm CMOS technology, uses this technique and demonstrates low phase-noise performance of -112.9-dBc/Hz at 1-MHz offset and FOMT of -187.4-dBc/Hz, which is the highest FOMT so far reported in regard to CMOS VCOs operating above 25 GHz.

In this paper, a low-complexity symbol-spaced turbo frequency domain equalization (FDE) algorithm based on Laurent decomposition is proposed for precoded binary continuous phase modulation (CPM) with modulation index h=1/2. At the transmitter, a precoder is utilized to eliminate the inherent memory of the CPM signal. At the receiver, a matched filter based on Laurent decomposition is utilized to make the detection symbol-spaced. As a result, the symbol-spaced iteration can be taken between the equalizer and the decoder directly without a CPM demodulator, and we derive a symbol-spaced soft interference cancellation frequency domain equalization (SSIC-FDE) algorithm for binary CPM with h=1/2. A new data block structure for FDE of partial response CPM is also presented. The computational complexity analysis and simulations show that this approach provides a complexity reduction and an impressive performance improvement over previously proposed turbo FDE algorithm for binary CPM with h=1/2 in multi-path fading channels.