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  • DualMotion: Global-to-Local Casual Motion Design for Character Animations

    Yichen PENG  Chunqi ZHAO  Haoran XIE  Tsukasa FUKUSATO  Kazunori MIYATA  Takeo IGARASHI  

     
    PAPER

      Pubricized:
    2022/12/07
      Vol:
    E106-D No:4
      Page(s):
    459-468

    Animating 3D characters using motion capture data requires basic expertise and manual labor. To support the creativity of animation design and make it easier for common users, we present a sketch-based interface DualMotion, with rough sketches as input for designing daily-life animations of characters, such as walking and jumping. Our approach enables to combine global motions of lower limbs and the local motion of the upper limbs in a database by utilizing a two-stage design strategy. Users are allowed to design a motion by starting with drawing a rough trajectory of a body/lower limb movement in the global design stage. The upper limb motions are then designed by drawing several more relative motion trajectories in the local design stage. We conduct a user study and verify the effectiveness and convenience of the proposed system in creative activities.

  • APVAS: Reducing the Memory Requirement of AS_PATH Validation by Introducing Aggregate Signatures into BGPsec

    Ouyang JUNJIE  Naoto YANAI  Tatsuya TAKEMURA  Masayuki OKADA  Shingo OKAMURA  Jason Paul CRUZ  

     
    PAPER

      Pubricized:
    2023/01/11
      Vol:
    E106-A No:3
      Page(s):
    170-184

    The BGPsec protocol, which is an extension of the border gateway protocol (BGP) for Internet routing known as BGPsec, uses digital signatures to guarantee the validity of routing information. However, the use of digital signatures in routing information on BGPsec causes a lack of memory in BGP routers, creating a gaping security hole in today's Internet. This problem hinders the practical realization and implementation of BGPsec. In this paper, we present APVAS (AS path validation based on aggregate signatures), a new protocol that reduces the memory consumption of routers running BGPsec when validating paths in routing information. APVAS relies on a novel aggregate signature scheme that compresses individually generated signatures into a single signature. Furthermore, we implement a prototype of APVAS on BIRD Internet Routing Daemon and demonstrate its efficiency on actual BGP connections. Our results show that the routing tables of the routers running BGPsec with APVAS have 20% lower memory consumption than those running the conventional BGPsec. We also confirm the effectiveness of APVAS in the real world by using 800,000 routes, which are equivalent to the full route information on a global scale.

  • Short Lattice Signature Scheme with Tighter Reduction under Ring-SIS Assumption

    Kaisei KAJITA  Go OHTAKE  Kazuto OGAWA  Koji NUIDA  Tsuyoshi TAKAGI  

     
    PAPER

      Pubricized:
    2022/09/08
      Vol:
    E106-A No:3
      Page(s):
    228-240

    We propose a short signature scheme under the ring-SIS assumption in the standard model. Specifically, by revisiting an existing construction [Ducas and Micciancio, CRYPTO 2014], we demonstrate lattice-based signatures with improved reduction loss. As far as we know, there are no ways to use multiple tags in the signature simulation of security proof in the lattice tag-based signatures. We address the tag-collision possibility in the lattice setting, which improves reduction loss. Our scheme generates tags from messages by constructing a scheme under a mild security condition that is existentially unforgeable against random message attack with auxiliary information. Thus our scheme can reduce the signature size since it does not need to send tags with the signatures. Our scheme has short signature sizes of O(1) and achieves tighter reduction loss than that of Ducas et al.'s scheme. Our proposed scheme has two variants. Our scheme with one property has tighter reduction and the same verification key size of O(log n) as that of Ducas et al.'s scheme, where n is the security parameter. Our scheme with the other property achieves much tighter reduction loss of O(Q/n) and verification key size of O(n), where Q is the number of signing queries.

  • A Study of The Risk Quantification Method of Cyber-Physical Systems focusing on Direct-Access Attacks to In-Vehicle Networks

    Yasuyuki KAWANISHI  Hideaki NISHIHARA  Hideki YAMAMOTO  Hirotaka YOSHIDA  Hiroyuki INOUE  

     
    PAPER

      Pubricized:
    2022/11/09
      Vol:
    E106-A No:3
      Page(s):
    341-349

    Cyber-physical systems, in which ICT systems and field devices are interconnected and interlocked, have become widespread. More threats need to be taken into consideration when designing the security of cyber-physical systems. Attackers may cause damage to the physical world by attacks which exploit vulnerabilities of ICT systems, while other attackers may use the weaknesses of physical boundaries to exploit ICT systems. Therefore, it is necessary to assess such risks of attacks properly. A direct-access attack in the field of automobiles is the latter type of attacks where an attacker connects unauthorized equipment to an in-vehicle network directly and attempts unauthorized access. But it has been considered as less realistic and evaluated less risky than other threats via network entry points by conventional risk assessment methods. We focused on reassessing threats via direct access attacks in proposing effective security design procedures for cyber-physical systems based on a guideline for automobiles, JASO TP15002. In this paper, we focus on “fitting to a specific area or viewpoint” of such a cyber-physical system, and devise a new risk quantification method, RSS-CWSS_CPS based on CWSS, which is also a vulnerability evaluation standard for ICT systems. It can quantify the characteristics of the physical boundaries in cyber-physical systems.

  • Multi Deletion/Substitution/Erasure Error-Correcting Codes for Information in Array Design

    Manabu HAGIWARA  

     
    PAPER-Coding Theory and Techniques

      Pubricized:
    2022/09/21
      Vol:
    E106-A No:3
      Page(s):
    368-374

    This paper considers error-correction for information in array design, i.e., two-dimensional design such as QR-codes. The error model is multi deletion/substitution/erasure errors. Code construction for the errors and an application of the code are provided. The decoding technique uses an error-locator for deletion codes.

  • Combinatorial Structures Behind Binary Generalized NTU Sequences

    Xiao-Nan LU  

     
    LETTER-Cryptography and Information Security

      Pubricized:
    2022/06/15
      Vol:
    E106-A No:3
      Page(s):
    440-444

    This paper concentrates on a class of pseudorandom sequences generated by combining q-ary m-sequences and quadratic characters over a finite field of odd order, called binary generalized NTU sequences. It is shown that the relationship among the sub-sequences of binary generalized NTU sequences can be formulated as combinatorial structures called Hadamard designs. As a consequence, the combinatorial structures generalize the group structure discovered by Kodera et al. (IEICE Trans. Fundamentals, vol.E102-A, no.12, pp.1659-1667, 2019) and lead to a finite-geometric explanation for the investigated group structure.

  • Orthogonal Variable Spreading Factor Codes Suppressing Signal-Envelope Fluctuation

    Tomoko K. MATSUSHIMA  Shoichiro YAMASAKI  Hirokazu TANAKA  

     
    LETTER-Spread Spectrum Technologies and Applications

      Pubricized:
    2022/08/08
      Vol:
    E106-A No:3
      Page(s):
    445-449

    Recently, complex orthogonal variable spreading factor (OVSF) codes based on polyphase orthogonal codes have been proposed to support multi-user/multi-rate data transmission services in synchronous direct-sequence code-division multiple access (DS-CDMA) systems. This study investigates the low signal-envelope fluctuation property of the complex OVSF codes in terms of transmission signal trajectories. In addition, a new method is proposed to suppress the envelope fluctuation more strongly at the expense of reducing the number of spreading sequences of the codes.

  • Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing

    Yutaka MASUDA  Yusei HONDA  Tohru ISHIHARA  

     
    PAPER

      Pubricized:
    2022/09/02
      Vol:
    E106-A No:3
      Page(s):
    514-522

    Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This work focuses on the verification where the computational results can be observed, the computational quality can be calculated from computational results, and the constraint of computational quality is given and defined as the constraint which is set to the computational quality of designed AC circuit with given workloads. Then, this paper proposes a novel dynamic verification framework of the AC circuit. The key idea of the proposed framework is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed framework additionally embeds the Design Under Verification (DUV) component into the calculation part of computational quality. Thanks to the DUV integration, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed framework and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed framework achieved 3.85 to 10.36 times higher coverage than the random test.

  • An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing

    Lingxiao HOU  Yutaka MASUDA  Tohru ISHIHARA  

     
    PAPER

      Pubricized:
    2022/09/02
      Vol:
    E106-A No:3
      Page(s):
    532-541

    The approximate logarithmic multiplier proposed by Mitchell provides an efficient alternative for processing dense multiplication or multiply-accumulate operations in applications such as image processing and real-time robotics. It offers the advantages of small area, high energy efficiency and is suitable for applications that do not necessarily achieve high accuracy. However, its maximum error of 11.1% makes it challenging to deploy in applications requiring relatively high accuracy. This paper proposes a novel operand decomposition method (OD) that decomposes one multiplication into the sum of multiple approximate logarithmic multiplications to widely reduce Mitchell multiplier errors while taking full advantage of its area savings. Based on the proposed OD method, this paper also proposes an accuracy reconfigurable multiply-accumulate (MAC) unit that provides multiple reconfigurable accuracies with high parallelism. Compared to a MAC unit consisting of accurate multipliers, the area is significantly reduced to less than half, improving the hardware parallelism while satisfying the required accuracy for various scenarios. The experimental results show the excellent applicability of our proposed MAC unit in image smoothing and robot localization and mapping application. We have also designed a prototype processor that integrates the minimum functionality of this MAC unit as a vector accelerator and have implemented a software-level accuracy reconfiguration in the form of an instruction set extension. We experimentally confirmed the correct operation of the proposed vector accelerator, which provides the different degrees of accuracy and parallelism at the software level.

  • Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design

    Shinichi NISHIZAWA  Toru NAKURA  

     
    PAPER

      Pubricized:
    2022/09/13
      Vol:
    E106-A No:3
      Page(s):
    551-559

    We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.

  • Sub-Signal Channel Modulation for Hitless Redundancy Switching Systems

    Takahiro KUBO  Yuhei KAWAKAMI  Hironao ABE  Natsuki YASUHARA  Hideo KAWATA  Shinichi YOSHIHARA  Tomoaki YOSHIDA  

     
    PAPER-Network System

      Pubricized:
    2022/09/12
      Vol:
    E106-B No:3
      Page(s):
    221-229

    This paper proposes a sub-signal channel modulation scheme for hitless redundancy switching systems that offers highly confidential communications. A hitless redundancy switching system prevents frame loss by using multiple routes to forward the same frame. Although most studies on redundancy switching systems deal with frame duplication, elimination, and selection of redundant paths for the main signal, we focus on the transmission of the sub-signal channel. We introduce mathematical expressions to model the transmission rate and bit error rate of the sub-signal channel. To evaluate the validity of the models, we conduct numerical simulations to calculate the sub-signal transmission rate, main-signal transmission rate, and bit error rate of the sub-signal channel at physical transmission rates of 100Mb/s, 1Gb/s, and 10Gb/s. We discuss how to design sub-signal channel modulation on the basis of the evaluation results. We further discuss applications of sub-signal modulation in terms of network size and jitter.

  • A Study of Phase-Adjusting Architectures for Low-Phase-Noise Quadrature Voltage-Controlled Oscillators Open Access

    Mamoru UGAJIN  Yuya KAKEI  Nobuyuki ITOH  

     
    PAPER-Electronic Circuits

      Pubricized:
    2022/08/03
      Vol:
    E106-C No:2
      Page(s):
    59-66

    Quadrature voltage-controlled oscillators (VCOs) with current-weight-average and voltage-weight-average phase-adjusting architectures are studied. The phase adjusting equalizes the oscillation frequency to the LC-resonant frequency. The merits of the equalization are explained by using Leeson's phase noise equation and the impulse sensitivity function (ISF). Quadrature VCOs with the phase-adjusting architectures are fabricated using 180-nm TSMC CMOS and show low-phase-noise performances compared to a conventional differential VCO. The ISF analysis and small-signal analysis also show that the drawbacks of the current-weight-average phase-adjusting and voltage-weight-average phase-adjusting architectures are current-source noise effect and large additional capacitance, respectively. A voltage-average-adjusting circuit with a source follower at its input alleviates the capacitance increase.

  • A SOM-CNN Algorithm for NLOS Signal Identification

    Ze Fu GAO  Hai Cheng TAO   Qin Yu ZHU  Yi Wen JIAO  Dong LI  Fei Long MAO  Chao LI  Yi Tong SI  Yu Xin WANG  

     
    PAPER-Fundamental Theories for Communications

      Pubricized:
    2022/08/01
      Vol:
    E106-B No:2
      Page(s):
    117-132

    Aiming at the problem of non-line of sight (NLOS) signal recognition for Ultra Wide Band (UWB) positioning, we utilize the concepts of Neural Network Clustering and Neural Network Pattern Recognition. We propose a classification algorithm based on self-organizing feature mapping (SOM) neural network batch processing, and a recognition algorithm based on convolutional neural network (CNN). By assigning different weights to learning, training and testing parts in the data set of UWB location signals with given known patterns, a strong NLOS signal recognizer is trained to minimize the recognition error rate. Finally, the proposed NLOS signal recognition algorithm is verified using data sets from real scenarios. The test results show that the proposed algorithm can solve the problem of UWB NLOS signal recognition under strong signal interference. The simulation results illustrate that the proposed algorithm is significantly more effective compared with other algorithms.

  • Learning Sparse Graph with Minimax Concave Penalty under Gaussian Markov Random Fields

    Tatsuya KOYAKUMARU  Masahiro YUKAWA  Eduardo PAVEZ  Antonio ORTEGA  

     
    PAPER-Graphs and Networks

      Pubricized:
    2022/07/01
      Vol:
    E106-A No:1
      Page(s):
    23-34

    This paper presents a convex-analytic framework to learn sparse graphs from data. While our problem formulation is inspired by an extension of the graphical lasso using the so-called combinatorial graph Laplacian framework, a key difference is the use of a nonconvex alternative to the l1 norm to attain graphs with better interpretability. Specifically, we use the weakly-convex minimax concave penalty (the difference between the l1 norm and the Huber function) which is known to yield sparse solutions with lower estimation bias than l1 for regression problems. In our framework, the graph Laplacian is replaced in the optimization by a linear transform of the vector corresponding to its upper triangular part. Via a reformulation relying on Moreau's decomposition, we show that overall convexity is guaranteed by introducing a quadratic function to our cost function. The problem can be solved efficiently by the primal-dual splitting method, of which the admissible conditions for provable convergence are presented. Numerical examples show that the proposed method significantly outperforms the existing graph learning methods with reasonable computation time.

  • Intelligent Dynamic Channel Assignment with Small-Cells for Uplink Machine-Type Communications

    Se-Jin KIM  

     
    LETTER-Mobile Information Network and Personal Communications

      Pubricized:
    2022/06/27
      Vol:
    E106-A No:1
      Page(s):
    88-91

    This letter proposes a novel intelligent dynamic channel assignment (DCA) scheme with small-cells to improve the system performance for uplink machine-type communications (MTC) based on OFDMA-FDD. Outdoor MTC devices (OMDs) have serious interference from indoor MTC devices (IMDs) served by small-cell access points (SAPs) with frequency reuse. Thus, in the proposed DCA scheme, the macro base station (MBS) first measures the received signal strength from both OMDs and IMDs after setting the transmission power. Then, the MBS dynamically assigns subchannels to each SAP with consideration of strong interference from IMDs to the MBS. Through simulation results, it is shown that the proposed DCA scheme outperforms other schemes in terms of the capacity of OMDs and IMDs.

  • A Novel e-Cash Payment System with Divisibility Based on Proxy Blind Signature in Web of Things

    Iuon-Chang LIN  Chin-Chen CHANG  Hsiao-Chi CHIANG  

     
    PAPER-Information Network

      Pubricized:
    2022/09/02
      Vol:
    E105-D No:12
      Page(s):
    2092-2103

    The prosperous Internet communication technologies have led to e-commerce in mobile computing and made Web of Things become popular. Electronic payment is the most important part of e-commerce, so many electronic payment schemes have been proposed. However, most of proposed schemes cannot give change. Based on proxy blind signatures, an e-cash payment system is proposed in this paper to solve this problem. This system can not only provide change divisibility through Web of Things, but also provide anonymity, verifiability, unforgeability and double-spending owner track.

  • Ground Test of Radio Frequency Compatibility for Cn-Band Satellite Navigation and Microwave Landing System Open Access

    Ruihua LIU  Yin LI  Ling ZOU  Yude NI  

     
    PAPER-Satellite Communications

      Pubricized:
    2022/05/19
      Vol:
    E105-B No:12
      Page(s):
    1580-1588

    Testing the radio frequency compatibility between Cn-band Satellite Navigation and Microwave Landing System (MLS) has included establishing a specific interference model and reporting the effect of such interference. This paper considers two interference scenarios according to the interfered system. By calculating the Power Flux Density (PFD) values, the interference for Cn-band satellite navigation downlink signal from several visible space stations on MLS service is evaluated. Simulation analysis of the interference for MLS DPSK-data word signal and scanning signal on Cn-band satellite navigation signal is based on the Spectral Separation Coefficient (SSC) and equivalent Carrier-to-Noise Ratio methodologies. Ground tests at a particular military airfield equipped with MLS ground stations were successfully carried out, and some measured data verified the theoretical and numerical results. This study will certainly benefit the design of Cn-band satellite navigation signals and guide the interoperability and compatibility research of Cn-band satellite navigation and MLS.

  • A Novel Fixed-Point Conversion Methodology For Digital Signal Processing Systems

    Phuong T.K. DINH  Linh T.T. DINH  Tung T. TRAN  Lam S. PHAM  Han Le DUC  Chi P. HOANG  Minh D. NGUYEN  

     
    PAPER-Digital Signal Processing

      Pubricized:
    2022/06/17
      Vol:
    E105-A No:12
      Page(s):
    1537-1550

    Recently, most signal processing algorithms have been developed with floating-point arithmetic, while the fixed-point arithmetic is more popular with most commercial devices and low-power real-time applications which are implemented on embedded/ASIC/FPGA systems. Therefore, the optimal Floating-point to Fixed-point Conversion (FFC) methodology is a promising solution. In this paper, we propose the FFC consisting of signal grouping technique and simulation-based word length optimization. In order to evaluate the performance of the proposed technique, simulations are carried out and hardware co-simulation on Field Programmable Gate Arrays (FPGAs) platform have been applied to complex Digital Signal Processing (DSP) algorithms: Linear Time Invariant (LTI) systems, multi-mode Fast Fourier Transform (FFT) circuit for IEEE 802.11 ax WLAN Devices and the calibration algorithm of gain and clock skew in Time-Interleaved ADC (TI-ADC) using Adaptive Noise Canceller (ANC). The results show that the proposed technique can reduce the hardware cost about 30% while being able to maintain its speed and reliability.

  • Accurate Doppler Velocity Estimation by Iterative WKD Algorithm for Pulse-Doppler Radar

    Takumi HAYASHI  Takeru ANDO  Shouhei KIDERA  

     
    PAPER-Sensing

      Pubricized:
    2022/06/29
      Vol:
    E105-B No:12
      Page(s):
    1600-1613

    In this study, we propose an accurate range-Doppler analysis algorithm for moving multiple objects in a short range using microwave (including millimeter wave) radars. As a promising Doppler analysis for the above model, we previously proposed a weighted kernel density (WKD) estimator algorithm, which overcomes several disadvantages in coherent integration based methods, such as a trade-off between temporal and frequency resolutions. However, in handling multiple objects like human body, it is difficult to maintain the accuracy of the Doppler velocity estimation, because there are multiple responses from multiple parts of object, like human body, incurring inaccuracies in range or Doppler velocity estimation. To address this issue, we propose an iterative algorithm by exploiting an output of the WKD algorithm. Three-dimensional numerical analysis, assuming a human body model in motion, and experimental tests demonstrate that the proposed algorithm provides more accurate, high-resolution range-Doppler velocity profiles than the original WKD algorithm, without increasing computational complexity. Particularly, the simulation results show that the cumulative probabilities of range errors within 10mm, and Doppler velocity error within 0.1m/s are enhanced from 34% (by the former method) to 63% (by the proposed method).

  • Novel Configuration for Phased-Array Antenna System Employing Frequency-Controlled Beam Steering Method

    Atsushi FUKUDA  Hiroshi OKAZAKI  Shoichi NARAHASHI  

     
    PAPER-Microwaves, Millimeter-Waves

      Pubricized:
    2022/06/10
      Vol:
    E105-C No:12
      Page(s):
    740-749

    This paper presents a novel frequency-controlled beam steering scheme for a phased-array antenna system (PAS). The proposed scheme employs phase-controlled carrier signals to form the PAS beam. Two local oscillators (LOs) and delay lines are used to generate the carrier signals. The carrier of one LO is divided into branches, and then the divided carriers passing through the corresponding delay lines have the desired phase relationship, which depends on the oscillation frequency of the LO. To confirm the feasibility of the scheme, four-branch PAS transmitters are configured and tested in a 10-GHz frequency band. The results verify that the formed beam is successfully steered in a wide range, i.e., the 3-dB beamwidth of approximately 100 degrees, using LO frequency control.

61-80hit(2667hit)