We fabricated Fe-silicide nanodots (NDs) on an ultrathin SiO2 layer and evaluated changes in electron transport properties with and without magnetic field application. High-density NDs with an areal density as high as ∼1011cm-2 were formed on thermally grown SiO2 by exposing ultrathin Fe/Si-NDs structures to a remote H2 plasma without external heating. In electron transport properties related to current-time characteristics for a diode with Fe electrode and charging energy to NDs, clear changes in current levels through NDs and electron injection modulation of NDs depending on intensity of magnetic fields were observed.

In this paper, the effects of the TiN encapsulating layer and the dopant segregation process on the interface properties and the Schottky barrier height reduction of PdEr-silicide/n-Si(100) were investigated. The results show that controlling the initial location of the boron dopants by adding the TiN encapsulating layer lowered the Schottky barrier height (SBH) for hole to 0.20 eV. Furthermore, the density of interface states (Dit) on the order of 1011eV-1cm-2 was obtained indicating that the dopant segregation process with TiN encapsulating layer effectively annihilated the interface states.

In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500°C/20 min in N2/4.9%H2 ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p+/n-Si(100) and n+/p-Si(100) such as 9.4×10-9Ωcm2 and 4.8×10-9Ωcm2, respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

We investigated the low temperature formation of Pd2Si on Si(100) with TiN encapsulating layer formed at 500°C/1 min. Furthermore, the dopant segregation process was performed with ion dose of 1x1015 cm-2 for B+. The uniform Pd2Si was successfully formed with low sheet resistance of 10.4 Ω/sq. Meanwhile, the PtSi formed on Si(100) showed rough surface morphology if the silicidation temperature was 500°C. The estimated Schottky barrier height to hole of 0.20 eV (qφBp) was realized for n-Si(100).

In this paper, we have investigated the PdEr-silicide formation utilizing a developed PdEr-alloy target for sputtering, and evaluated the contact resistivity of PdEr-silicide layer formed on n-Si(100) by dopant segregation process for the first time. Pd2Si and ErSi2 have same hexagonal structure, while the Schottky barrier height for electron (Φbn) is different as 0.75 eV and 0.28 eV, respectively. A 20 nm-thick PdEr-alloy layer was deposited on the n-Si(100) substrates utilizing a developed PdEr-alloy target by the RF magnetron sputtering at room temperature. Then, 10 nm-thick TiN encapsulating layer was in-situ deposited at room temperature. Next, silicidation was carried out by the RTA at 500 for 5 min in N2/4.9%H2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, qΦbn was reduced from 0.75 eV of Pd2Si to 0.43 eV of PdEr-silicide. Furthermore, 4.0x10-8Ωcm2 was extracted for the PdEr-silicide to n-Si(100) by the dopant segregation process.

In this paper, we have investigated the characteristics of PdYb-silicide layer formed by the silicidation of Pd/Yb/n-Si(100) stacked structures for the first time. Pd (12-20 nm)/Yb (0-8 nm) stacked layers were deposited on n-Si(100) substrates by the RF magnetron sputtering at room temperature. Then, 10 nm-thick HfN encapsulating layer was deposited at room temperature. Next, silicidation was carried out by the RTA at 500°C/1 min in N2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, Schottky barrier height (SBH) for electron was reduced from 0.73 eV of Pd2Si to 0.4 eV of PdYb-silicide in case the Pd/Yb thicknesses were 14/6 nm, respectively.

We have investigated PtHf silicide formation utilizing a developed PtHf-alloy target to realize low contact resistivity for the first time. A 20 nm-thick PtHf-alloy thin film was deposited on the n-Si(100) by RF magnetron sputtering at room temperature. Then, silicidation was carried out by rapid thermal annealing (RTA) system at 450-600°C/5 min in N2/4.9%H2 ambient. The PtHf-alloy silcide, PtHfSi, layers were successfully formed, and the Schottky barrier height (SBH) for electron of 0.45 eV was obtained by 450°C silicidation. Furthermore, low contact resistivity was achieved for fabricated PtHSi such as 8.4x10-8 Ωcm2 evaluated by cross-bridge Kelvin resistor (CBKR) method.

We have fabricated MOS capacitors with a hybrid floating gate (FG) consisting of Ni silicide nanodots (NiSi-NDs) and silicon-quantum-dots (Si-QDs) and studied electron transfer characteristics in the hybrid FG structures induced by the irradiation of 1310 nm light. The flat-band voltage shift due to the charging of the hybrid FG under light irradiation was lower than that in the dark. The observed optical response can be attributed to the shift of the charge centroid in the hybrid FG caused by the photoexcitation of electrons in NiSi-NDs and their transfer to Si-QDs. The photoexcited electron transfer from the NiSi-NDs to the Si-QDs in response to pulsed gate voltages was also evaluated from the increase in transient current caused by the light irradiation. The amount of transferred charge is likely to increase in proportion to pulse gate voltage.

We investigated solid-phase growth reactions for the fabrication of β-FeSi2 films from Fe and FeSi sources by reflection high-energy electron diffraction (RHEED). To enhance the interdiffusion of Fe and Si for the growth of β-FeSi2, the use of FeSi instead of pure Fe as the source for the initial deposition was examined. The RHEED observation during the solid phase reaction indicated that the growth temperature was markedly decreased to 390 K using the FeSi source. We discuss the reaction mechanism of the solid phase growth of β-FeSi2 from Fe and FeSi sources in this paper.

In order to reduce PtSi Schottky barrier height (SBH) for electron, we investigated modulation of PtSi work function by alloying with low work function metal, such as Hf (3.9 eV) and Yb (2.7 eV). Pt (10-20 nm)/Hf, Yb (0-10 nm)/n-Si(100) stacked structures were in-situ deposited at room temperature by RF magnetron sputtering method. In case of PtxHf1 - xSi formed at 400/60 min annealing in N2, SBH for electron was reduced from 0.85 eV to 0.53 eV with Hf thickness without increase of sheet resistance. Yb incorporation also affected the SBH modulation, however, the sheet resistance increased with increase of Yb thickness.

Effects of Fe/Si ratio and growth temperature were investigated in order to realize high quality Fe3Si/Ge structures. It was found that very small χmin values (2-3%) were achieved in a wide temperature range of 60-200 under the stoichiometric condition. From TEM observation, it was rvealed that the Fe3Si/Ge structures with atomically flat interfaces were realized. In addition, thermal stability of the Fe3Si/Ge structures was guaranteed up to 400. These results suggested that growth at a low temperature (<200) under the stoichiometric condition was essential to obtain high quality Fe3Si/Ge structures with sharp interfaces.

A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes

The role of electric field in metal-induced lateral crystallization (MILC) of amorphous Si (a-Si) under limited Ni-supply condition has been investigated. The nominal lateral-growth rate was increased from 3.6 µm/h (no-electric field) to 23 µm/h at the positive electrode side and reduced to 2.8 µm/h at the negative electrode side in presence of the electric field of 20 V/cm. However, spontaneously nucleated needle-like Si crystals were observed in the enhanced positive electrode side, which have been found to be independent of the MILC. Further investigation under the condition where Ni in the supply region was removed on the way of crystallization revealed that the electric field enhanced crystallization greatly reduced. These results indicate that the electric field does not enhance the MILC growth but enhances the diffusion of Ni in a-Si which takes place prior to the MILC growth.

We report on the analysis and fabrication of vertical PtSi Schottky source/drain metal oxide semiconductor field effect transistors (MOSFETs), which are suitable for combination with quantum effect devices such as resonant tunneling diodes. Analysis was carried out by one-dimensional approximation of the device structure, WKB approximation of the tunneling probability in Schottky barrier tunneling and self-consistent calculation. Theoretical calculation showed good drivability (750 µA/µm) of this device with tOX = 1 nm and tSi = 5 nm. As a preliminary experiment, devices with a Si channel thickness of 8 nm, 20 nm or 30 nm and a vertical channel length of 55 nm were fabricated. Although the drain current at the "on" state was small due to the thick gate oxide of 8 nm, analysis and measurement showed reasonable agreement with respect to the drivability. Based on the results of theoretical analysis, the device drivability can be much improved by reducing the gate oxide thickness.

Amorphous silicon thin film transistors(a-Si TFTs) with a channel-etched structure were fabricated. The key technologies to realize these simple-process TFTs were 1) fabricating data lines and pixel electrodes of indium tin oxide(ITO); 2) carrying out tapered dry etching of plural layers of the a-Si and gate insulator silicon nitide; and 3) forming silicide layer to reduce the contact resistance between the phosphorousdoped a-Si and ITO. Excellent image quality, with a high contrast ratio of more than 100: 1, was obtained for video graphic array(VGA) mode TFT-LCDs using a dot inversion driving method. Furthermore, the transmission distribution was uniform with less than a 4.5% deviation on the whole display area although the ITO data line resistances were as large as 120 kΩ per line.

A two-dimensional self-aligned silicide (SALICIDE) model has been developed using the general-purpose process simulator OPUS. A new two-dimensional growth model is proposed. Utilizing a newly-difined effective silicide thickness, the model accounts both silicon-diffusion and metal-diffusion limited silicide growth. Silicide lateral-growth along a sidewall spacer is successfully simulated for Si-diffusion limited silicide growth. Complete MOSFET process simulation with a SALICIDE process is demonstrated for the first time.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.