In this paper, we report a reduction in the access resistance of InP/InGaAs composite-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a back-source electrode. The source region has two electrodes. The source electrode on the surface side is connected to the channel through a doped layer and supplies the electrons. The back-source electrode is constructed under the channel layer and is insulated from the doped layer in order to avoid current leakage. The function of the back-source electrode is to increase the carrier concentration in the channel layer of the source region. In the simulation, the electron density in the channel layer is almost doubled by the effect of the back-source voltage. The fabricated III-V MOSFET has a channel length of 6 µm. A 6% increase in the maximum drain current density (Id) and a 6.8% increase in the transconductance (gm) (Vd = 2 V) are observed. The increase in the carrier density in the channel is estimated to be 20% when the applied voltage of the back-source electrode is 6 V.

In this letter, we propose a novel resource allocation scheme to enhance downlink system performance for orthogonal frequency division multiple access (OFDMA) and time division duplex (TDD) based femtocell networks. In the proposed scheme, the macro base station (mBS) and femto base stations (fBSs) service macro user equipments (mUEs) and femto user equipments (fUEs) in inner and outer zones in different periods to reduce interference substantially. Simulations show the proposed scheme outperforms femtocell networks with fractional frequency reuse (FFR) systems in terms of the system capacity and outage probability for mUEs and fUEs.

As an add-on device option for the ultra-low power CMOS technology, the double-gated vertical-channel Tunnel Field-Effect Transistors (TFETs) of different source configurations are comparatively studied from the perspectives of fabrication and current drivability. While the top-source design where the source of the device is placed on the top of the fin makes the fabrication and source engineering much easier, it is more susceptible to parasitic resistance issue. The bottom-source design is difficult to engineer the tunneling barrier and may require a special replacement technique. Examples of the schemes to engineer the tunneling barrier for the bottom-source TFET are suggested. A TCAD simulation study on the bottom-source devices shows that both the parasitic resistance of source region and the current enhancement mechanism by field coupling need be carefully considered in designing the source.

The Liquid-crystal display (LCD) overdrive technique has been utilized to reduce motion blur on a display via a reduction in the response time. However, to measure the variation of the pixel amplitudes, it is necessary to store the previous frame using a large frame memory. To downscale the frame memory, block truncation coding (BTC) is commonly employed due to the simplicity of its implementation, even if some visual artifacts may occur for image blocks with high frequency components. In this paper, we present a multimode-multilevel BTC (MBTC) technique that improves performance while maintaining simplicity. To improve the visual quality, we uniquely determine the quantization level and coding mode of each block according to the distribution of the luminance and chrominance amplitudes. For a compression ratio of 6:1, the proposed method demonstrates higher coding efficiency and overdrive performance by up to 3.81 dB in the PSNR compared to other methods.

In this paper, Source/Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750 µA/µm at σS/D = 2 nm/dec. and σLDD=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60 nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100 nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100 nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.

Applying Distributed Video Coding (DVC) to mobile devices that have limited computation and power resources can be a very challenging problem due to its high-complexity decoding. To address this, this paper proposes a DVC bitstream organizer. The proposed DVC bitstream organizer reduces the complexity associated with repetitive channel decoding and SI generation in a flexible manner. It allows users to choose a means of minimizing the computational complexity of the DVC decoder according to their preferences and the device's resource limitations. An experiment shows that the proposed method increases decoding speeds by up to 25 times.

This paper proposes a new biquad structure based on a flipped voltage follower (FVF) for low-power and wide-bandwidth (BW) low pass filter. The proposed biquad structure consists of an FVF and a source follower (SF) for complex pole pair generation and zero cancellation. The presented design provides good linearity at low power consumption, owing to the voltage follower structures. A power/BW ratio (PBWR) is suggested as a performance metric to compare power efficiency to bandwidth, and the proposed biquad structure shows excellent PBWR, especially for low quality factor (Q) design. As a prototype, a fourth order Bessel filter was fabricated in 0.18 µm CMOS technology. The measured BW, power consumption, IIP3, and FoM are 120 MHz, 180 µW, 15 dBm, and 0.34 fJ, respectively.

In this paper, we investigate the performance of Thorup's algorithm by comparing it to Dijkstra's algorithm for large-scale network simulations. One of the challenges toward the realization of large-scale network simulations is the efficient execution to find shortest paths in a graph with N vertices and M edges. The time complexity for solving a single-source shortest path (SSSP) problem with Dijkstra's algorithm with a binary heap (DIJKSTRA-BH) is O((M + N) log N). An sophisticated algorithm called Thorup's algorithm has been proposed. The original version of Thorup's algorithm (THORUP-FR) has the time complexity of O(M + N). A simplified version of Thorup's algorithm (THORUP-KL) has the time complexity of O(M α(N) + N) where α(N) is the functional inverse of the Ackerman function. In this paper, we compare the performances (i.e., execution time and memory consumption) of THORUP-KL and DIJKSTRA-BH since it is known that THORUP-FR is at least ten times slower than Dijkstra's algorithm with a Fibonaccii heap. We find that (1) THORUP-KL is almost always faster than DIJKSTRA-BH for large-scale network simulations, and (2) the performances of THORUP-KL and DIJKSTRA-BH deviate from their time complexities due to the presence of the memory cache in the microprocessor.

This paper proposed three channel aggregation schemes for cognitive radio networks, a constant channel aggregation scheme, a probability distribution-based variable channel aggregation scheme, and a residual channel-based variable channel aggregation scheme. A cognitive radio network can have a wide bandwidth if unused channels in the primary networks are aggregated. Channel aggregation schemes involve either constant channel aggregation or variable channel aggregation. In this paper, a Markov chain is used to develop an analytical model of channel aggregation schemes; and the performance of the model is evaluated in terms of the average sojourn time, the average throughput, the forced termination probability, and the blocking probability. Simulation results show that channel aggregation schemes can reduce the average sojourn time of cognitive users by increasing the channel occupation rate of unused channels in a primary network.

We propose a new cognitive radio network architecture using the IP multimedia subsystem (IMS) functionality. We implement the cognitive radio network entities standardized in IEEE 1900.4 on the IMS that exchanges RAN and terminal context information between the networks and the terminals to make optimum and immediate reconfiguration decisions. In our proposed architecture, RAN context information is obtained from cellular networks which are directly connected to the IMS. The presence management functions of the IMS are applied to exchange those information in a “push” manner, which enables immediate notification of changes in wireless environment. We evaluate the performance of the proposed context information exchange method, by comparing with the cases that adequate and immediate RAN context information is not available. The evaluation results show that the proposed framework gives 10–30% superior performance than the conventional cognitive radio networks.

Non-negative matrix factorization (NMF) is widely used for monaural musical sound source separation because of its efficiency and good performance. However, an additional clustering process is required because the musical sound mixture is separated into more signals than the number of musical tracks during NMF separation. In the conventional method, manual clustering or training-based clustering is performed with an additional learning process. Recently, a clustering algorithm based on the mel-frequency cepstrum coefficient (MFCC) was proposed for unsupervised clustering. However, MFCC clustering supplies limited information for clustering. In this paper, we propose various timbre features for unsupervised clustering and a clustering algorithm with these features. Simulation experiments are carried out using various musical sound mixtures. The results indicate that the proposed method improves clustering performance, as compared to conventional MFCC-based clustering.

This paper describes a method for estimating Direction Of Arrival (DOA) of multiple sound sources in full azimuth with three microphones. Estimating DOA with paired microphone arrays creates imaginary sound sources because of time delay of arrival (TDOA) being identical between real and imaginary sources. Imaginary sound sources can create chronic problems in multiple Sound Source Localization (SSL), because they can be localized as real sound sources. Our proposed approach is based on the observation that each microphone array creates imaginary sound sources, but the DOA of imaginary sources may be different depending on the orientation of the paired microphone array. With the fact that a real source would always be localized in the same direction regardless of the array orientation, we can suppress the imaginary sound sources by minimum filtering based on Steered Response Power – Phase Transform (SRP-PHAT) method. A set of experiments conducted in a real noisy environment showed that the proposed method was accurate in localizing multiple sound sources.

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0 V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7 V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400 mV.

In this letter, a novel resource allocation method is proposed for Discrete Fourier Transform Spread Orthogonal Frequency Division Multiple Access (DFT-s-OFDMA) systems in Long Term Evolution (LTE). The proposed method is developed based on a minimal metric loss criterion and performs better than the commonly used Recursive Maximum Expansion (RME) method.

This letter studies cellular controlled short-range communication in OFDMA networks. The network needs to decide when to allow direct communication between a closely located device-to-device (D2D) pair instead of conveying data from one device to the other via the base station and when not to, in addition to subchannel and power allocation. Our goal is to maximize the total network throughput while guaranteeing the rate requirements of all users. For that purpose, we formulate an optimization problem subject to subchannel and power constraints. A scheme which combines a joint mode selection and subchannel allocation algorithm based on equal power allocation with a power reallocation scheme is proposed. Simulation results show that our proposed scheme can improve the network throughput and outage probability compared with other schemes.

This paper proposes a utility function-based scheduling algorithm for integrated real-time and non-real-time services in long-term evolution systems. The proposed utility function satisfies the target dropping ratio of real-time users; it uses the delay constraint and increases the throughput of non-real-time users by scheduling real-time users together with non-real-time users. Simulation results show that the proposed scheduling algorithm significantly improves the throughput of non-real-time users without sacrificing the quality of service of real-time users.

In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.

In this letter, we introduce two different resource allocation and Tx power management schemes, called resource control and fixed power (RCFP) and fixed resource and power control (FRPC), in an LTE-Advanced femtocell network. We analyze and compare the two schemes in terms of the system throughput for downlink and energy consumption of home evolved NodeB (HeNB) Tx power according to the number of HeNBs and home user equipment (HUE)'s user traffic density (C). The simulation results show that the FRPC scheme has better performance in terms of system throughput for macro user equipments (MUEs) and energy consumption in low C.

We study joint rate control and resource allocation with a packet collision constraint that maximizes the total utility of secondary users in cognitive radio networks. We formulate and decouple the original optimization problem into separable subproblems and then develop an algorithm that converges to optimal rate control and resource allocation. The proposed algorithm can operate on different time-scales to reduce the amortized time complexity.

This paper proposes a combinatorial auction-based marketplace mechanism for cloud computing services, which allows users to reserve arbitrary combination of services at requested timeslots, prices and quality of service. The proposed mechanism helps enterprise users build workflow applications in a cloud computing environment, specifically on the platform-as-a-service, where the users need to compose multiple types of services at different timeslots. The proposed marketplace mechanism consists of a forward market for an advance reservation and a spot market for immediate allocation of services. Each market employs mixed integer programming to enforce a Pareto optimum allocation with maximized social economic welfare, as well as double-sided auction design to encourage both users and providers to compete for buying and selling the services. The evaluation results show that (1) the proposed forward/combinatorial mechanism outperforms other non-combinatorial and/or non-reservation (spot) mechanisms in both user-centric rationality and global efficiency, and (2) running both a forward market and a spot market improves utilization without disturbing advance reservations depending on the provider's policy.