A security-tagged architecture is one that applies tags on data to detect attack or information leakage, tracking data flow. The previous studies using security-tagged architecture mostly focused on how to utilize tags, not how the tags are implemented. A naive implementation of tags simply adds a tag field to every byte of the cache and the memory. Such a technique, however, results in a huge hardware overhead. This paper proposes a low-overhead tagged architecture. We achieve our goal by exploiting some properties of tag, the non-uniformity and the locality of reference. Our design includes the use of uniquely designed multi-level table and various cache-like structures, all contributing to exploit these properties. Under simulation, our method was able to limit the memory overhead to 0.685%, where a naive implementation suffered 12.5% overhead.

A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.

In this letter, the performance of opportunistic-based two-way relaying with beamforming over Nakagami-m fading channels is investigated. We provide an approximate expression for the cumulative distribution function of the end-to-end signal-to-noise ratio to derive the closed-form lower bounds for the outage probability and average bit error probability as well as the closed-form upper bound for the ergodic capacity. Simulation results demonstrate the tightness of the derived bounds.

This paper presents a voltage reference that utilizes the virtually diode-connected MOS transistors, biased in the weak-inversion region. The proposed architecture increases the gain of the feedback loop that consequently reduces the system sensitivity, and hence improves the PSRR. The circuit is designed and simulated in a standard 0.18 µm CMOS technology. The simulation results in HSPICE indicate the successful operation of the circuit as follows: the PSRR at DC frequency is 86 dB and for the temperature range from -55C to 125C, the variation of the output reference voltage is less than 66 ppm/C.

While volunteer computing (VC) systems reach the most powerful computing platforms, they still have the problem of guaranteeing computational correctness, due to the inherent unreliability of volunteer participants. Spot-checking technique, which checks each participant by allocating spotter jobs, is a promising approach to the validation of computation results. The current spot-checking is based on the implicit assumption that participants never distinguish spotter jobs from normal ones; however generating such spotter jobs is still an open problem. Hence, in the real VC environment where the implicit assumption does not always hold, spot-checking-based methods such as well-known credibility-based voting become almost impossible to guarantee the computational correctness. In this paper, we generalize spot-checking by introducing the idea of imperfect checking. This generalization allows to guarantee the computational correctness under the situation that spot-checking is not fully-reliable and participants may distinguish spotter jobs. Moreover, we develop a generalized formula of the credibility, which enables credibility-based voting to utilize check-by-voting technique. Simulation results show that check-by-voting improves the performance of credibility-based voting, while guaranteeing the same level of computational correctness.

The selection cooperation is a basic and attractive scheme of cooperative diversity in the multiple relays scenario. Most previous schemes of selection cooperation consist only one relay-stage in which one relay is selected to retransmit, and the signal from the selected relay is not utilized by other relays. In this paper, we introduce a two relay-stage selection cooperation scheme. The performance can be improved by letting all other relays to utilize the signal from the first selected relay to make another selection and retransmission in the second relay-stage. We derive the closed-form expression of the outage probability of the proposed scheme in the high SNR regime. Both theoretical and numerical results suggest that the proposed scheme can reduce the outage probability compared with the traditional scheme with only one relay-stage. Furthermore, we demonstrate that more than two relay-stage can not further reduce the outage probability. We also study the dependence of the proposed scheme on stage lengths and topology, and analyze the increased overhead.

A low voltage operational active inductor circuit is attractive for spiral-inductor-less LNA because of realizing high gain and low voltage operation simultaneously. In this paper, a simply structured low-voltage operational active inductor to enhance the amplifier gain is introduced and analyzed. This active inductor, which utilizes a transistor load operated in the triode region and a source follower, features a small DC voltage drop suitable for low voltage LNAs. An LNA using the active inductor load was designed with an input matching circuit using 90 nm CMOS technology. The LNA tuned to 2.4 GHz operation has 19.5 dB of the internal gain. In addition, the frequency characteristics are easily varied by changing the capacitance value in the active inductor circuit. The core circuit occupies only 0.0026 mm2 and consumes 2.8 mW with 1.2 V supply voltage.

In this letter, we analyze the outage performance of decode-and-forward relay systems with imperfect MRC receiver at the destination. Unlike the conventional perfect MRC, the weight of each branch of the imperfect MRC receiver is only the conjugate of the channel impulse response, not being normalized by the noise variance. We derive an exact closed-form expression for the outage probability over dissimilar Nakagami-m fading channels. Various numerical examples confirm the proposed analysis.

Recently, novel full-diversity full-rate quasi-orthogonal space-time block codes (QSTBCs) with power scaling and double-symbol maximum likelihood (ML) decoding was proposed. Specifically, the codes can achieve full-diversity through linearly combining two adequately power scaled orthogonal space-time block codes (OSTBCs). In this letter, we derive expressions for mutual information and post-processing signal-to-noise ratio (SNR) for a system with four transmit antennas. By exploiting these formulas, we propose three transmit antenna grouping (TAG) methods for a closed-loop system with low-rate feedback information. The TAG methods make it possible to provide an excellent error-rate performance even with a low-complexity zero-forcing (ZF) detection, especially in spatially correlated fading channels.

This paper describes a least complex, high speed decoding method named multi-stage threshold decoding (MTD-DR). Each stage of MTD-DR is formed by the traditional threshold decoder with a special shift register, called difference register (DR). After flipping each information bit, DR helps to shorten the Hamming and the Euclidian distance between a received word and the decoded codeword for hard and soft decoding, respectively. However, the MTD-DR with self-orthogonal convolutional codes (SOCCs), type 1 in this paper, makes an unavoidable error group, which depends on the tap connection patterns in the encoder, and limits the error performance. This paper introduces a class of SOCCs type 2 which can breakdown that error group, as a result, MTD-DR gives better error performance. For a shorter code (code length = 4200), hard and soft decoding MTD-DR achieves 4.7 dB and 6.5 dB coding gain over the additive white Gaussian noise (AWGN) channel at the bit error rate (BER) 10-5, respectively. In addition, hard and soft decoding MTD-DR for a longer code (code length = 80000) give 5.3 dB and 7.1 dB coding gain under the same condition, respectively. The hard and the soft decoding MTD-DR experiences error flooring at high Eb/N0 region. For improving overall error performance of MTD-DR, this paper proposes parity check codes concatenation with soft decoding MTD-DR as well.

This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.

In this letter, a dual-hop wireless communication network with opportunistic amplify and forward (O-AF) relay is investigated over independent and non-identically distributed Nakagami-m fading channels. Employing Maclaurin series expansion around zero to derive the approximate probability density function of the normalized instantaneous signal-to-noise ratio (SNR), the asymptotic symbol error rate (SER) and outage probability expressions are presented. Simulation results indicate that the derived expressions well match the results of Monte-Carlo simulations at medium and high SNR regions. By comparing the O-AF with all AF relaying analyzed previously, it can be concluded that the former has significantly better performance than the latter in many cases.

CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.

In this paper, we analyze the performance of the 21 Alamouti scheme suggested by Alamouti, composed of the transmit space-time code and the simple linear decoding processing, in perfectly time-varying and spatially correlated channels. We derive the closed-form probability density function (PDF) of output signal-to-noise ratio (SNR) and outage probability of the Alamouti scheme as a function of spatial correlation coefficient in the consideration of no correlation in time. We observe that the performance of the Alamouti scheme is severely degraded when the channels are time-varying and spatially correlated.

The principles for good design of battery-aware voltage scheduling algorithms for both aperiodic and periodic task sets on dynamic voltage scaling (DVS) systems are presented. The proposed algorithms are based on greedy heuristics suggested by several battery characteristics and Lagrange multipliers. To construct the proposed algorithms, we use the battery characteristics in the early stage of scheduling more properly. As a consequence, the proposed algorithms show superior results on synthetic examples of periodic and aperiodic tasks from the task sets which are excerpted from the comparative work, on uni- and multi-processor platforms, respectively. In particular, for some large task sets, the proposed algorithms enable previously unschedulable task sets due to battery exhaustion to be schedulable.

Single event transient (SET) effects on original static cascade voltage switch logic (CVSL) exclusive-OR (EX-OR) circuits have been investigated using SPICE. SET simulation results have confirmed that the static CVSL EX-OR circuits have increased tolerance to SET. The static CVSL EX-OR circuit is more than 200 times harder than the conventional CMOS circuit.

Gas flow in arc quenching chamber has an important effect on the interruption capability of low voltage circuit breakers. In this paper, based on a simplified model of arc chamber with a single break, which can be opened by the electro-dynamics repulsion force automatically, the effect of different vent configurations including middle vent and side vent on the interruption performance is investigated. First, the experiments are carried out to compare the different performance in the interruption process between middle vent type and side vent type. In addition, according to the experimental model, a 3-D magneto-hydrodynamic model was developed by adapting and modified the commercial computational fluid dynamics software FLUENT. The simulation results show the same trend in arc motion as explained in the experimental conclusions in theory.

High efficiency power feeding systems are effective solutions for reducing the ICT power consumption with reducing power consumption of the ICT equipment and cooling systems. A higher voltage direct current (HVDC) power feeding system prototype was produced. This system is composed of a rectifier equipment, power distribution unit, batteries, and the ICT equipment. The configuration is similar to a -48 V DC power supply system. The output of the rectifier equipment is 100 kW, and the output voltage is 401.4 V. This paper present the configuration of the HVDC power feeding system and discuss its basic characteristics in the prototype system.

Since a radio frequency identification (RFID) transponder (tag) generates both location and time information when it enters and leaves a reader, the trajectory of a moving, tagged object can be traced. Due to the time intervals between entries to successive readers, during which tags are not tracked, accurate tracing of complete trajectories can be difficult. To overcome this problem, we propose a tag trajectory indexing scheme called TR-tree (R-tree-based tag trajectory index) that can trace tags by combining the local trajectories at each reader. In experiments, this scheme showed superior performance compared with other indices.

A novel method is proposed that can estimate the tag population in Radio Frequency Identification (RFID) systems by using a Hadamard code for the tag response. We formulate the maximum likelihood estimator for the tag population using the number of observed footprints. The lookup table of the estimation algorithm has low complexity. Simulation results show that the proposed estimator performs considerably better than the conventional schemes.