This paper describes the characteristics of lithium-ion cells developed for stationary use, as in the case of stand-by sources in power systems. The effect of a cell-voltage-equalizing circuit developed for batteries of cells is also demonstrated. The tested lithium-ion cells were suitable to be charged by the constant-current, constant-voltage (CCCV) method and could be charged efficiently over a wide range of temperatures. They also showed good discharge performance with little dependence on the discharge current and temperature. Total capacity reduction of over 60% can be expected in batteries of lithium-ion cells. The cell-voltage-equalizing circuit was shown to be useful and necessary for batteries of lithium-ion cells in order to suppress deviations in the cell voltage and capacity loss.

This paper presents the novel method not only to suppress the input current harmonics but also to realize the low frequency output voltage ripple using the multiple-input ac-dc converter, which is considered from viewpoints of the relatively small power application and simple circuit configuration. The operation principle and control strategy of the proposed circuit are discussed. As a result, it is clarified that the new circuit has excellent performance characteristics such as high power factor over 0.99, low total harmonic current distortion factor less than 9.2% and low output voltage ripple of 40 mV.

This paper is devoted to simulate the arc movement in the quenching chamber of the low-voltage circuit breaker. Based on a group of governing equations, a three-dimensional (3-D) arc model is built and solved by a modified commercial code. According to the simulated results, some phenomena such as a 'bulge' in front of the arc column, a tail in the rear of the arc column, arc shrinkage near the electrodes and arc movement characteristics versus different chamber configuration and external magnetic field are found, and the mechanism of the above phenomena is described in detail. Finally, in order to verify the simulation results, arc movement is investigated by hi-spec motion analyzer experimentally.

It is interesting to resolve coherent signals impinging upon a linear sensor array with low computational complexity in array signal processing. In this paper, a computationally efficient method of signal subspace fitting (SSF) for direction-of-arrival (DOA) estimation is developed, based on the multi-stage wiener filter (MSWF). To find the new signal subspace, the proposed method only needs to compute the matched filters in the forward recursion of the MSWF, does not involve the estimate of an array covariance matrix or any eigendecomposition, thus implying that the proposed method is computationally efficient. Numerical results show that the proposed method provides the comparable estimation accuracy with the classical weighted subspace fitting (WSF) method for uncorrelated signals at reasonably high SNR and reasonably large samples, and surpasses the latter for coherent signals in the case of low SNR and small samples. When SNR is low and the samples are small, the proposed method is less accurate than the classical WSF method for uncorrelated signals. This drawback is balanced by the computational advantage of the proposed method.

The exact calculation of the ergodic and outage capacity for Rayleigh fading single-input multiple-output (SIMO) channels in the presence of unequal-power Rayleigh fading interferers is mathematically quite challenging due to the complicated distribution of the capacity. In this paper, a SIMO system with M receive antennas and N interferers is considered. Based on some statistical results, the closed-form upper and lower bound for the ergodic and outage capacity are derived respectively. These bounds are shown to be simple to compute and appear to be quite tight.

In this paper, a low-voltage low-power sigma-delta modulator dedicated to implantable sensing devices is presented. This second-order single-loop sigma-delta modulator is implemented with half-delay integrators. These integrators are based on new fully-differential CMOS class AB switched-Operational Transconductance Amplifier (switched-OTA). An on-chip voltage doubler is introduced to locally boost a supply voltage at the input stage of a conventional OTA in order to allow rail-to-rail signal swing. Experimental results of the modulator fabricated in CMOS 0.18 µm technology confirm its expected features of a peak signal-to-noise ratio (SNR) of 72 dB, a signal-to-noise distortion ratio (SNDR) of 62 dB in a 5 kHz signal bandwidth, and a power consumption lower than 66 µW with a 900 mV voltage supply.

In a CDMA non-linear interference canceller, a generated replica of an interference signal is multiplied by a positive number smaller than unity, which is called cancellation moderating factor (CMF), to prevent interference enhancement due to inaccurate replica subtraction. In this paper, two CMF controlling schemes applicable to a multistage parallel interference canceller with multi-antenna (spatial diversity) reception are proposed. They control CMF by using the mean square error of the complex channel gain or by using the ratio of the estimated power of each interference signal to remaining interference signals' power, in order to mitigate the replica subtraction error due to inaccurate channel estimation. The performance of the proposed schemes are evaluated by computer simulations assuming an asynchronous uplink single chip-rate variable spreading factor DS-CDMA system. The simulation results show that the proposed schemes with higher order diversity reception improve the bit error rate (BER) performance compared with a conventional scheme considering the tentative decision error or fixed CMF settings. Their performance improvement is by 0.1-0.9 dB in terms of the required Eb/N0 at an average BER of 10-5 over exponentially decaying 5-path Rayleigh distributed channels when the number of receiving antennas is 6.

This paper presents a new multistage comb-rotated sinc (RS) decimator with a sharpened magnitude response. Novelty of this paper is that the multistage structure has more design parameters that provides additional flexibility to the design procedure. It uses different sharpening polynomials and different cascaded comb filters at different stages. As the comb filters at the latter stages are of lower order than that of the original comb filter, the use of more complex sharpening polynomials at latter stages is possible. This leads to an improvement of the frequency characteristic without a significant increase in the complexity of the overall filter. The comb filter of the first stage is realized in a non-recursive form and can be implemented in a computationally efficient form by making use of the polyphase decomposition of the transfer function in which the subfilters operate at a lower rate that depends on the down-sampling factor employed in the first stage. In addition, both multipliers of the rotated sinc (RS) filter of the second stage work at a lower rate.

The conditional sum adder (CSA) has been shown to outperform other adders applied in high-speed applications. This investigation proposes a modified CSA called the conditional carry adder (CCA). Based on the proposed adder architecture, six 64-bit hybrid dual-threshold CCAs for power-aware applications were discussed. Architectural modification of the CCA raises the operation speed, decreases the power dissipation, and lowers the hardware overhead. The proposed 64-bit CCA can decrease the number of multiplexers and internal nodes in the adder design by around 27% compared to the 64-bit CSA. Furthermore, components on critical paths use a low threshold voltage to accelerate the speed of operation, and other components use the normal threshold voltage to save power. This feature is very useful in implementing power-aware arithmetic systems. One of the proposed circuits has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.

A series-fed beam-scanning array employing a MUlti-Stage Configured microstrip Antenna with Tunable reactance devices (MUSCAT) is proposed. The proposed antenna significantly expands the beam scanning range and achieves high efficiency. This antenna comprises unit element groups, whose elements are placed close to each other and employ tunable reactance devices. Analyses and experiments on the unit element groups show that their multi-stage configuration extends the phase shift range and increases the radiation efficiency, e.g., a 120phase shift and the radiation efficiency of more than 50% are achieved, when three stages are employed. The radiation pattern of the fabricated MUSCAT array antenna comprising eight unit element groups is measured. A beam scanning range of 27, which is greater than twice the beam scanning range of a non-multi-stage configuration, is achieved.

A structure of a track-and-hold (T/H) circuit based on a pair of complementary floating-gate (FG) MOS transistors is introduced. Its main features include low complexity, low operating supply voltage and gain insensitivity to device mismatches, leading to efficient realization of numerous baseband functions in modern communication systems. The detailed operation and performance analysis of the FG T/H circuit are given. Functional verification of the circuit is provided through a breadboard experiment. The effectiveness of the circuit is verified via simulations where the single T/H cell operating at 10 MHz clock frequency exhibits gain variation less than 0.13% and a dynamic range over 71 dB with the coupling capacitance of 300 fF at 1.5 V supply and 12.75 µW power consumption. As a demonstration on its practical viability, the designed FG T/H cell was also utilized to realize a 10 MS/s 7-tap analog correlator for possible use in modern communication applications.

This paper proposes two high-performance multi-threshold-voltage CMOS (MTCMOS) F/Fs that are based on the CMOS hybrid-latch F/F and the CMOS semi-dynamic F/F. The proposed F/Fs utilize a clock-gating technique or a data recovery circuit in order to preserve their logic states in the power-down mode. They can change operation modes whether the clock level is high or low, and they provide outputs to fanouts in the power-down mode. When compared with existing clock-free MTCMOS F/Fs, the proposed MTCMOS hybrid-latch F/F shows maximum reduction of average delay, average power, and average power-delay product by 33%, 46%, and 63% for the supply voltage ranging from 0.8 V to 1.2 V. Although outperformed by the MTCMOS hybrid-latch F/F, the proposed MTCMOS semi-dynamic F/F inherits the benefit of the embedded logic from the CMOS SD F/F. Experimental results indicate that the MTCMOS semi-dynamic F/F can be used to implement a logic circuit that is superior to the one designed using the MTCMOS hybrid-latch F/F in speed, power, and area.

A pure CMOS threshold-voltage reference (VTR) circuit achieves temperature (T) coefficient of 5 µV/(T = -60+100) and supply voltage (VDD) sensitivity of 0.1 mV/V (VDD = 35 V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant VTR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm2 in the TEG (Test Element Group) chip fabricated by 1.2 µm n-well CMOS process.

In a switched-capacitor (SC) circuit, the major block is an operational transconductance amplifier (OTA) designed in order to form a feedback loop. However, the OTA is the block that consumes most of the power in SC circuits. This paper proposes the use of a class-C inverter instead of the OTA in SC circuits and a corresponding switches configuration for extremely low power applications. A detailed analysis and design trade-offs are also provided. Simulation and experimental results show that sufficient performance can be obtained even though a class-C inverter is used. The second-order biquad filter and the second-order SC sigma-delta (ΣΔ) modulator based on a class-C inverter are designed. These circuits have been fabricated with a 0.35-µm CMOS process. The measurement results of the fabricated SC biquad filter show a 59-dB signal-to-noise-plus-distortion ratio (SNDR) for a 0.2-Vp-p input signal and 0.9-V dynamic ranges. The power consumption of the biquad filter is only 0.4 µW with a 1-V power supply. The measurement results of the fabricated ΣΔ modulator show a 61-dB peak SNR for a 1.6-kHz bandwidth with a sample rate of 200 kHz. The modulator consumes 0.8 µW with a 1-V power supply.

In this paper, a detailed model of a hybrid dual-stage Raman/erbium-doped fiber (EDF) amplifier is presented. This model takes into account the impact of double Rayleigh backscattering (DRB) noise, amplified spontaneous emission (ASE) noise and Kerr-nonlinearity induced impairments in the amplification process. Using this model, we present a comprehensive analysis of the operation of hybrid dual-stage Raman/EDF amplifiers under above impairments. We show that under fixed total gain conditions for the amplifier module, high Raman gain causes the introduction of increased DRB noise to the amplified signals whereas low Raman gain causes the introduction of high ASE noise power through EDF amplifier. Therefore a balance between the Raman amplifier gain and EDF amplifier gain is required for optimal operation. These observations are then combined to show an optimization process, which could be applied to improve the design of hybrid dual-stage Raman/EDF amplifiers.

In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 µm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.

A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V VDD. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-µm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields.

For the power amplifier used in CDMA cellular phones, the supply voltage is switched between high and low at a transmission power several decibels higher than 10 dBm using a DC-DC converter to improve operational efficiency. The longer the operation time under low supply voltage, the lower the current consumption of the cellular phone. In order to increase the output power under low supply voltage, we applied the 2nd harmonic-injection technique, which is useful for distortion compensation. With 2nd harmonic-injection, there is an inflectional power point. The distortion increases rapidly when output power goes beyond the inflectional power point. It is important to make this inflectional power point high in order to compensate for distortion in the high output-power region. We report here that the inflectional power point can be increased by connecting a 2nd harmonic short circuit to the drain terminal of the FET to which the 2nd harmonic for distortion compensation is injected. A prototype of the final stage of the power amplifier under a supply voltage of Vdd=1.5 V is presented. We report that applying a CDMA uplink signal, 1.5 dB higher output power and 12% higher drain efficiency is achieved compared when only 2nd harmonic injection is employed.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at VCE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm2. The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.