A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18 µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3 V to 1.8 V. The current consumption of voltage detection, standby current, is changed from 65 pA for Vin = 0.3 V to 5.5 µA for Vin = 1.8 V. The thermal characteristics from 250 K to 400 K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4 ppm/K and that in saturation region is 10 ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.

We consider the problem of secret key agreement in Gaussian Maurer's Model. In Gaussian Maurer's model, legitimate receivers, Alice and Bob, and a wire-tapper, Eve, receive signals randomly generated by a satellite through three independent memoryless Gaussian channels respectively. Then Alice and Bob generate a common secret key from their received signals. In this model, we propose a protocol for generating a common secret key by using the result of soft-decision of Alice and Bob's received signals. Then, we calculate a lower bound on the secret key rate in our proposed protocol. As a result of comparison with the protocol that only uses hard-decision, we found that the higher rate is obtained by using our protocol.

In this paper, we derive the average bit error probability (BEP) for common digital modulation schemes and the outage probability of double Nakagami-m channels with MRC diversity. First, the probability density function (PDF) and moment generating function (MGF) of received signal with maximal ratio combining (MRC) receiver diversity are computed. The derived MGF results are simplified in terms of a generalized hypergeometric function 2F0. The derived BEP expressions find applications in existing wireless systems such as satellite mobile communication system, mobile-to-mobile communication system and multiple-input multiple-output (MIMO) wireless communication system. In addition, the obtained general MGF expression considers combined Rayleigh Nakagami-m, double Rayleigh, single Rayleigh, single Nakagami-m, and non-fading or additive white Gaussian noise (AWGN) channels as special cases. The simulation results agree well with the theoretical results.

Recently a framework called Tag-KEM/DEM was introduced to construct efficient hybrid encryption schemes. Although it is known that generic encode-then-encrypt construction of chosen ciphertext secure public-key encryption also applies to secure Tag-KEM construction and some known encoding method like OAEP can be used for this purpose, it is worth pursuing more efficient encoding method dedicated for Tag-KEM construction. This paper proposes an encoding method that yields efficient Tag-KEM schemes when combined with set partial one-way permutations such as RSA and Rabin's encryption scheme. To our knowledge, this leads to the most practical hybrid encryption scheme of this type. We also present an efficient Tag-KEM which is CCA-secure under general factoring assumption rather than Blum factoring assumption.

A cell planning and resource allocation scheme called EBRD (Enhanced Bandwidth and Region Division) is presented for improving channel capacity and for maintaining a proper QoS (Quality of Service) over the downlink OFDMA (Orthogonal Frequency Division Multiple Access) system. Through an optimal combination of sectorization and frequency overlay, the EBRD scheme improves both channel capacity and outage probability. In order to analyze the performance of the proposed algorithm, the outage probability is obtained as a closed numerical form. In the simulation, the EBRD scheme outperforms 3-sectorization in terms of throughput and outage probability.

The sub-threshold R-MOSFET resistor structure which enables tuning range extension below the threshold voltage in the MOSFET with moderate to weak inversion operation is analyzed in detail. The principal operation of the sub-threshold resistor is briefly described. The analysis of its characteristic based on approximations of a general MOS equation valid for all regions is given along with discussion on design implication and consideration. Experiments and simulations are provided to validate the theoretical analysis and design, and to verify the feasibility at a supply voltage as low as 0.5 V using a low-threshold devices in a 1.8-V 0.18 µm CMOS process.

The control of the organic field-effect transistor characteristics is necessary to produce the integrated circuits using organic semiconductors. Variations in the poly (3-hexylthiophene) field-effect transistor characteristics upon post-treatment such as thermal treatment and voltage treatment in N2 atmosphere have been investigated. The controllability and reproducibility of the threshold voltage and mobility were achieved as a result of the post-treatments.

In a multi-user orthogonal frequency division multiplexing (OFDM) system, efficient resource allocation is required to provide service to more users. In this letter, we propose an improved subcarrier allocation algorithm that can increase the spectral efficiency and the number of total transmission bits even if the number of users is too large. The proposed algorithm is divided into two stages. In the first stage, a group of users who are eligible for services is determined by using the bit error rate (BER), the users' minimum data rate requirement, and channel information. In the second stage, subcarriers are first allocated to the users on the basis of channel state, and then the reallocation is performed so that resource waste is minimized. We show that the proposed algorithm outperforms the conventional one on the basis of outage probability, spectral efficiency, and the number of total transmission bits through a computer simulation.

In this letter, we first provide the closed-form exact outage probability of opportunistic single relay selection in decode-and-forward (DF) relaying with the direct source-destination link under arbitrarily distributed Rayleigh fading channels. The signals from the source and the selected relay are combined at the destination by using maximal ratio combining (MRC). We derive the probability density function (PDF) and the cumulative density function (CDF) of received SNR at the destination. Numerical results show that the analytic results exactly match with the simulated ones.

A novel voltage level controller for low-power charge pump converters will be presented in this paper. The proposed voltage level controller would react according to the pumped voltage in the charge-transfer-switch (CTS) converter. For the CTS circuit, the pumping operation would be degraded by the charge sharing effect in the auxiliary switch path. In this study, a voltage shifter was used as the voltage level controller to overcome this serious problem without consuming too much chip area. The simulation results showed that the converter can accept a rated input of 1.5 V and generated an output up to 8 V based on the TSMC 0.35-µm CMOS technology. The layout consumed an area of 125*160 µm2. The highest output obtained in measuring the real chip was 5.5 V which is primarily due to the limitation that the transistor could tolerated. The largest load was estimated as high as 6 mW which is large enough for on-chip application.

In this letter, two OTAs with MOSFETs operating in the weak inversion region are proposed. One of the OTAs uses the exponential-logarithm transformation algorithm. Furthermore, the other realizes the high-linearity characteristics due to a small fluctuation of the common-terminal voltage of differential pair. The performance of the proposed OTAs was confirmed by HSPICE simulation.

This paper studies a dual-hop amplify-and-forward (AF) relaying systems over shadowed Nakagami-m fading channels and derives an approximate analytical expression for the outage probability. The numerical results show that the derived analytical expression can provide very well approximations to the simulation results.

In real-time embedded systems, there is requirement for adapting both energy consumption and Quality of Services (QoS) of tasks according to their importance. This paper proposes an adaptive power-aware resource allocation method to resolve a trade-off between the energy consumption and QoS levels according to their importance with guaranteeing fairness. The proposed resource allocator consists of two components: the total resource optimizer to search for the optimal total resource and QoS-fairness-based allocator to allocate resource to tasks guaranteeing the fairness. These components adaptively achieve the optimal resource allocation formulated by a nonlinear optimization problem with the time complexity O(n) for the number of tasks n even if tasks' characteristics cannot be identified precisely. The simulation result shows that the rapidness of the convergence of the resource allocation to the optimal one is suitable for real-time systems with large number of tasks.

In this letter, we investigate the outage performance for decode-and-forward relaying under Rayleigh fading in the presence of multiple unequal-powered Rayleigh co-channel interferers. A close-form expression for the outage probability is derived and simulation results verify the theoretical solution.

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back- interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the "medium-thickness" poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back- threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front- gate biases. We evaluated the front- and back- interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back- interface trap densities for both samples in initial state are around 51011 to 1.31012 cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

A novel electronically tunable high input impedance voltage-mode multifunction filter with single inputs and three outputs employing two single-output-operational transconductance amplifiers, one differential difference current conveyor and two capacitors is proposed. The presented filter can be realized the highpass, bandpass and lowpass functions, simultaneously. The input of the filter exhibits high input impedance so that the synthesized filter can be cascaded without additional buffers. The circuit needs no any external resistors and employs two grounded capacitors, which is suitable for integrated circuit implementation.

This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3 dB up to 250 MSample/s and a 0.8 VPP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2 µm standard CMOS technology, and a wide range of operation between 1 nW and 100 µW was demonstrated. The accuracy of the voltage follower was 30 mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10 mV. The temperature dependence of the output was 0.11 mV/. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10 mV accuracy and the cell size is 105.3µm 81.4 µm in 1.2 µm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2 mV in a range of total current between 3 nA and 10 µA and in a temperature range between 30 and 100.

Multiple supply voltage (MSV) is an effective scheme to achieve low power. Recent works in MSV are based on physical level and aim at reducing physical overheads, but all of them do not consider level converter, which is one of the most important issues in dual-vdd design. In this work, a logic and layout aware methodology and related algorithms combining voltage assignment and placement are proposed to minimize the number of level converters and to implement voltage islands with minimal physical overheads. Experimental results show that our approach uses much fewer level converters (reduced by 83.23% on average) and improves the power savings by 16% on average compared to the previous approach [1]. Furthermore, the methodology is able to produce feasible placement with a small impact to traditional placement goals.

In this letter a new structure of multifunctional frequency filter using a universal voltage conveyor (UVC) is presented. The multifunctional circuit can realize a low-pass, high-pass and band-pass filter. All types of frequency filter can be realized as inverting or non-inverting. Advantages of the proposed structure are the independent control of the quality factor at the cut-off frequency and the low output impedance of output terminals. The computer simulations and measuring of particular frequency filters are depicted.