Using the transient current switch circuit in parallel with the energizing contacts, the slow decay of the contact current due to thermal fusion of metal was observed just after the contact voltage exceeded the melting contact voltage Um. At that time, the contact voltage was higher than the boiling contact voltage Ub. These results contradict Holm's θ theory. A new melting model of breaking mechanical contact is proposed. The area surrounding a cluster of contacting a-spots melts, the melt metal diffuses, and the contact spot thermally shrinks. Including the metal phase transition from solid to liquid, the increase of contact resistance is introduced to the electric circuit analysis. The numerical analysis agrees qualitatively with measured V-I characteristics.

This study utilizes a new adaptive sense current controller to get an accurate power supply. The proposed controller effectively reduces output ripple voltage of converters operated over the load current range. This reduction is realized using an adaptive sense current circuit that automatically adjusts the inductor current according to operational conditions. The proposed boost converter is designed and fabricated with a standard TSMC 3.3/5 V 0.35-µm 2P4M CMOS technology. The experimental results show that the power-conversion efficiency of the proposed boost converter is 2-5% higher than that of the conventional converter with a current-limited circuit. The proposed circuit greatly reduces (i.e. by 76%) output ripple voltage compared with the conventional circuit at a 10 mA loading current.

This paper presents a 1 V operating fully differential OTA using NMOS inverters in place of the traditional differential pair. To obtain high gain, a two-stage configuration is used in which the first stage has feedforward paths to cancel the common-mode signal, and the second stage has common-mode feedback paths to stabilize the output common-mode voltage. The proposed OTA was fabricated by an 0.18 µm CMOS technology. Measured gain is 40 dB and GBW is 10 MHz, in addition to differential output voltage swing of 1.8 Vp - p. It is confirmed that the proposed OTA can operate from 1 V power supply and has very large output swing capability even in a 1 V operation. The proposed OTA configuration contributes to a solution to the low power supply voltage issue in scaled CMOS analog circuits.

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

In this letter we investigate the relaying strategies for multihop transmission in wireless networks over Rayleigh fading channels. Theoretical analysis reveals that equally allocating power among all transmitters and placing relays equidistantly on the line between source and destination are optimal in terms of outage capacity. Then equal time duration for the transmission of each hop is also proved to be optimal. Furthermore, the optimum number of hops is also derived and shown to be inversely proportional to the signal-to-noise ratio (SNR). Numerical simulations agree well with the reported theoretical results.

To reduce RFID tag identification delay, we propose a novel Dynamic Splitting protocol (DS) which is an improvement of the Query tree protocol (QT). DS controls the number of branches of a tree dynamically. An improved performance of DS relative to QT is verified by analytical results and simulation studies.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

In this paper, a novel 800 mV beta-multiplier reference current source circuit is presented. In order to cope with the narrow input common-mode range of the Opamp in the reference circuit, the resistive voltage divider was employed. High gain Opamp was designed to compensate for the intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18 µm CMOS process with nominal Vth of 420 mV and -450 mV for n-MOS and p-MOS transistor, respectively. The total power consumption including Opamp is less than 50 µW.

An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.

A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.

A novel voltage measurement circuit which utilizes process variation is proposed. Using the proposed circuit, the voltage of a nonperiodic waveform at a particular time point can be accurately captured by a single clock pulse (one-shot measurement). The proposed circuit can be designed without compensation circuits against process variation, and thus occupies only a small area. An analytical expression of offset voltage for the comparator utilizing process variation (UPV-comparator), which plays a key role in the proposed circuit, is derived and design considerations for the proposed circuit are discussed. The circuit operation is confirmed through SPICE simulation using 90 nm CMOS device models. The -0.04 and -3 dB bandwidths (99% and 50% amplitudes) of the proposed circuit are about 10 MHz and far over 1 GHz, respectively. The circuit area is also estimated using an experimental layout.

CMOS circuits consume great dynamic power in switching. It has been proposed that energy transfer through a rising Vdd dissipates small amounts of energy. In typical power gate circuits, the high-performance PMOS transistors (PSW) that connect the circuit blocks to the power supply reduce leakage power by shutting off outer power (Vdd) to the idle blocks. We expand this technique by utilizing active PSW, which are turned on and off by clock signal. The PSW are fully turned on only for half of each clock cycle. This means that sufficient Vdd is provided to the circuit continuously for half of each clock cycle. In this manner, the circuit charge and discharge actions are cycle occur in different phases, and ramp Vdd is supplied to the designed circuit; we name this technique "CKVdd." CKVdd is a clock-controlled self-stabilized voltage technique, which generates stable ramp voltage to suppress the currents effectively. It is proposed to reduce dynamic power dissipation in conventional CMOS digital circuits. As compared to the conventional circuit, the circuits using CKVdd technique possesses several characteristics that differ from those of the current circuits using constant Vdd power source. First, CKVdd technique combines the power source and clock signal; it is an efficient low power technique. Second, CKVdd propose a feasible method to generate ramp-Vdd and low-Vdd. This technique would be convenient used to design generic low power digital circuits. Third, normal CMOS circuits show the dynamic power consumption increase proportional to the clock frequency. CKVdd results in a lower-than-usual frequency dependency, it is suitable used to design high clock speed circuits. In investigating constant Vdd for MPEG VLD decoders, CKVdd-circuit reduces 48% of the usual power dissipation and 88% of the usual peak current with small delay penalty.

Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

This letter proposes a mismatch insensitive switched-capacitor multiply-by-four (4X) amplifier using the voltage addition scheme. The proposed circuit provides 2-times faster speed and about half of silicon area when compared with the cascade of conventional 2X amplifiers. Monte-Carlo simulation results show about 15% gain accuracy improvement over the cascaded 2X- amplifiers.

In this letter, we propose a multi-cell cooperation method for broadcast packet transmission in the OFDM-based cellular system with multiple transmit antennas. In the proposed method, to transmit two streams of spatially demultiplexed or transmit diversity coded symbols, we divide a coded packet into subparts to each of which different cell group and antenna pairs are assigned. It is shown that the proposed method reduces the outage probability with only negligible increase in channel estimation.

In RFID systems, collision resolution is a significant issue in fast tag identification. This letter presents a dynamic frame-slotted ALOHA algorithm that uses a collision factor (DFSA-CF). This method enables fast tag identification by estimating the next frame size with the collision factor in the current frame. Simulation results show that the proposed method reduces slot times Required for RFID identification. When the number of tags is larger than the frame size, the efficiency of the proposed method is greater than those of conventional algorithms.

The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.

Analysis of cascading outages in power systems is important for understanding why large blackouts emerge and how to prevent them. Cascading outages are complex dynamics of power systems, and one cause of them is the interaction between swing dynamics of synchronous machines and protection operation of relays and circuit breakers. This paper uses hybrid dynamical systems as a mathematical model for cascading outages caused by the interaction. Hybrid dynamical systems can combine families of flows describing swing dynamics with switching rules that are based on protection operation. This paper refers to data on a cascading outage in the September 2003 blackout in Italy and shows a hybrid dynamical system by which propagation of outages reproduced is consistent with the data. This result suggests that hybrid dynamical systems can provide an effective model for the analysis of cascading outages in power systems.

In this letter, we propose a new scheme for the tag structure of the EPCglobal Class-1 Generation-2 (EPC C1 Gen2) standard equipped with a channel encoding block and the corresponding decoding block in the receiver of the reader system. The channel coded tag is designed to fully accommodate the EPC C1 Gen2 standard. The use of the proposed channel encoding block increases the number of logic gates in the tag by no more than 5%. The proposed reader system is designed to be used in the mixed tag modes as well, where the channel coded tags and existing tags co-exist in the same inventory round. The performances of the proposed tags and the corresponding reader systems are also presented by comparing the number of EPC error frames and the tag identification time with those of the conventional tags and reader systems.