In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signal and monolithic microwave integrated circuits. The InGaAs/InP DHBTs were grown by MBE and fabricated using conventional process techniques. Devices with an emitter junction area of 4.8 µm2 exhibited peak cutoff frequency (fT) and maximum oscillation frequency (fMAX) values of 265 and 305 GHz, respectively, and a breakdown voltage (BVCEo) of over 5 V. Using this technology, a set of mixed-signal IC building blocks for ≥ 80 Gbit/s fibre optical links, including distributed amplifiers (DA), voltage controlled oscillators (VCO), and multiplexers (MUX), have been successfully fabricated and operated at 80 Gbit/s and beyond.

Experimental result and theoretical analysis are reported for bias-voltage dependence of oscillation frequency in resonant tunneling diodes (RTDs) integrated with slot antennas. Frequency change of 18 GHz is obtained experimentally for a device with the central oscillation frequency of 470 GHz. The observed frequency change is attributed to the bias-voltage dependence of the transit time of electrons across the RTD layers, which results in a voltage-dependent capacitance added to RTD. Theoretical analysis taking into account this transit time is in reasonable agreement with the observed results. Voltage-controlled RTD oscillators in the terahertz range are expected from the theoretical results. A structure suitable for large frequency change is also discussed briefly.

Phase pure cubic (c-) GaN/AlGaN heterostructures on 3C-SiC free standing (001) substrates have successfully been developed. Almost complete (100%) phase pure c-GaN films are achieved with 2-nm surface roughness on 3C-SiC substrate and stoichiometric growth conditions. The polarization effect in c-GaN/AlGaN has been evaluated, based on measuring the transition energy of GaN/AlGaN quantum wells (QWs). It is demonstrated that the polarization electric fields are negligible small in c-GaN/AlGaN/3C-SiC compared with those of hexagonal (h-)GaN/AlGaN, 710 kV/cm for Al content x of 0.15, and 1.4 MV/cm for x of 0.25. A sheet carrier concentration of c-GaN/AlGaN heterojunction interface is estimated to 1.61012 cm-2, one order of magnitude smaller than that of h-GaN/AlGaN. The band diagrams of c-GaN/AlGaN HEMTs have been simulated to demonstrate the normally-off mode operation. The blocking voltage capability of GaN films was demonstrated with C-V measurement of Schottky diode test vehicle, and extrapolated higher than 600 V in c-GaN films at a doping level below 51015 cm-3, to show the possibility for high power electronics applications.

This investigation of the temperature and illumination effects on the AlGaN/GaN HFET threshold voltage shows that it shifts about -1 V under incandescent lamp or blue LED illumination, while almost no shift takes place under red LED illumination. The temperature coefficient for the threshold voltage shift is +3.44 mV/deg under the illuminations and +0.28 mV/deg in darkness. The threshold voltage variation can be attributed to a virtual back-gate effect caused by light-generated buffer layer potential variations. The expressions for the potential variation are derived using Shockley-Read-Hall (SRH) statistics and the Maxwell-Boltzmann distribution for the carriers and deep traps in the buffer layer. The expressions indicate that large photoresponses will occur when the electron concentration in the buffer layer is extremely small, that is, highly resistive. In semi-insulating substrates, the substrate potential varies so as to keep the trap occupation function constant. The sign and the magnitude of the threshold voltage variation are explained by the shift of the pinning energy calculated from the Fermi-Dirac distribution function.

Based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing (RTA), enhancement mode (E-mode) AlGaN/GaN HEMTs with low on-resistance and low knee-voltage were fabricated. The fabricated E-mode AlGaN/GaN HEMT with 1 µm-long gate exhibits a threshold voltage of 0.9 V, a knee-voltage of 2.2 V, a maximum drain current density of 310 mA/mm, a peak gm of 148 mS/mm, a current gain cutoff frequency fT of 10.1 GHz and a maximum oscillation frequency fmax of 34.3 GHz. In addition, the fluoride-based plasma treatment was also found to be effective in lowering the gate leakage current, in both forward and reverse bias. Two orders of magnitude reducation in gate leakage current was observed in the fabricated E-mode HEMTs compared to the conventional D-mode HEMTs without fluoride-based plasma treatment.

Multiple-input multiple-output (MIMO) systems applying macroscopic selection diversity (MSD) are analyzed in composite fading channels through derived expressions of capacity outage probability. The MSD system uses a maximum capacity MIMO base station (BS) selection algorithm, where the results show a significant improvement in outage capacity.

A method using an averaging technique for the analysis and evaluation of real quasi-resonant converters (QRC's) is proposed in this paper. To reduce the great difference between the real characteristics and those of ideal circuits, a modeling technique is developed by considering the effect of parasitic power losses. Then, using the averaging approach reasonably simplifies the process of solving equations to obtain the steady-state solutions of state variables. Also, an updating algorithm is constructed to take all the power losses such as core losses, which are often absent in the conventional analysis, into account to improve the accuracy of the steady-state solutions. By these efforts, the evaluation of characteristics for QRC's is realized.

This letter presents two high-performance level-converting flip-flops (LCFF) for multi-VDD systems, indirect precharging flip-flop (IPFF) and multi-supply complementary pass-transistor flip-flop (MCPFF). Employing a simple precharging scheme, IPFF provides high operating speed. MCPFF, on the other hand, provides low power operations by implementing the edge-triggering function with complementary pass transistors. Performance comparison indicates that IPFF operates at the highest speed and MCPFF consumes the lowest power among the seven LCFFs under evaluation.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.

The complexity of maximum-likelihood (ML) decoding for unitary space-time modulation (USTM) is exponential in the code rate times symbol periods. In this letter, we propose a new USTM scheme which consists of USTMs with noncoherent multistage decoding. The decoding of the proposed scheme is less complex than ML decoding. We also find some good codes of the proposed scheme according to the design criterion. Simulation results indicate that our codes perform better than seamless USTMs over the quasistatic fading channels.

The medium access control (MAC) protocol is the main determiner of the system throughput in Wireless Local Area Networks (WLANs). The MAC technique of the IEEE 802.11 protocol is called Distributed Coordination Function (DCF). DCF is based on a carrier sense multiple access with collision avoidance (CSMA/CA) scheme with binary slotted exponential backoff. Each station generates a random backoff interval before transmitting a packet to minimize the probability of collision with packets being transmitted by other stations. However, when the number of stations increases, the system throughput decreases. This paper proposes a new backoff algorithm that uses finish tags. The proposed algorithm uses the finish tag of each station to control the backoff intervals so as to improve system throughput. The finish tag is updated when a packet reaches the front of its flow, and it is attached to the packet just prior to transmission. When a station receives packets with older finish tags, its backoff time interval is increased. For this reason, the more the stations there are, the larger the backoff time becomes. Simulations confirm that the proposal improves system throughput of a IEEE 802.11 network under saturation conditions.

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 µm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.

Bi-stable displays form the foundation of a novel and attractive LCD technology. From now on, images can be maintained on the LCD after driving voltages have been withdrawn from the electrodes. In low frame-rate applications such as e-books, e-labels, smartcards etc., this offers a major improvement in power consumption and battery life. However, bi-stable displays require high driving voltages and complex waveforms. Furthermore, the nature of some applications doesn't allow the use of relatively large passive components. This rules out more traditional approaches for high-voltage generation with external coils or capacitors. This paper describes the design of completely integrated and programmable high-voltage generators capable of generating output voltages up to 50 V out of a 3 V supply voltage. Features like 8-bit output voltage programmability and stabilisation were implemented to make this type of high-voltage generator suitable for bi-stable display drivers. Design aspects and simulation results are discussed, as well as measurements on prototype generators implemented in the 0.7 µm 100 V I2T100 technology from AMI Semiconductor.

In software development, comprehensive software reviews and testings are important activities to preserve high quality and to control maintenance cost. However it would be actually difficult to perform comprehensive software reviews and testings because of a lot of components, a lack of manpower and other realistic restrictions. To improve performances of reviews and testings in object-oriented software, this paper proposes a novel model for detecting cost-prone classes; the model is based on Mahalanobis-Taguchi method--an extended statistical discriminant method merging with a pattern recognition approach. Experimental results using a lot of Java software are provided to statistically demonstrate that the proposed model has a high ability for detecting cost-prone classes.

The downlink (base-to-mobile) bit error rate (BER) performance for a mobile user with relatively weak received signal in a multicarrier-CDMA (MC-CDMA) cellular system can be improved by utilizing the site diversity reception. With joint use of MMSE-based frequency domain equalization (FDE) and antenna diversity combining, the site diversity operation will increase the downlink capacity. In this paper, an expression for the theoretical conditional BER for the given set of channel gains is derived based on Gaussian approximation of the interference components. The local average BER is then obtained by averaging the conditional BER over the given set of channel gains using Monte-Carlo numerical method. The outage probability is measured from the numerically obtained cumulative distribution of the local average BER to determine the downlink capacity. Results from theoretical computation are compared to the results from computer simulation and discussed.

Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.

The electrical parameters (88 LRGC matrices) of 8-coupled uniform lossy transmission lines were extracted from 40 S-parameter values measured by using 2-port VNA measurements, where all the ports other than 2 VNA ports were terminated by 50 ohm chip resistors. It was assumed in the extraction step that the transmission lines are weakly-coupled, and that the resistance values of all the termination chip resistors are exactly 50 ohms with the second reflections neglected. Comparison of the extracted LRGC matrix components with those from a commercial 3D field solver revealed on average and a maximum relative difference of 2.45% and 7.66%, respectively. In addition, the time-domain crosstalk voltage waveforms in the measured data and those in the SPICE simulation results using the extracted LRGC parameters agreed very well with the average difference and the maximum relative difference in peak crosstalk voltages of 4.15% and 9.68%, respectively.