A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-µm CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of 1 V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a new clocking technique.

This paper describes a sub-1-V power-supply, which is useful for self-powered short-range wireless systems with ambient energy sources. A variable-stage DC-DC converter, which consists of multi-stage switched capacitor circuits and has intermittent operation with an external capacitor, makes it possible to extend the time for self-powered operation. We fabricated a variable-stage DC-DC converter and an intermittent operation circuit with a 0.8-µm CMOS/SOI process. We also applied the sub-1-V power-supply system to a self-powered short-range wireless system and verified its effectiveness.

This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement- and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-Vth CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5 V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25-µm MTCMOS/SOI process. The frequency divider operates down to 0.3 V with a maximum operating frequency of 3.6 GHz while suppressing power dissipation to 0.3 mW. The 32-bit adder operates at a frequency of 1 GHz at 0.5 V.

To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.

We propose a novel Schottky barrier diode with a dual Schottky structure combined with an AlGaN/GaN heterostructure. The purpose of this diode was to lower the on-state voltage and to maintain the high reverse breakdown voltage. An AlGaN/GaN heterostructure was grown using a metalorganic chemical vapor deposition (MOCVD). The Schottky barrier diode with a dual Schottky structure was fabricated on the AlGaN/GaN heterostructure. As a result, the on-voltage of the diode was below 0.1 V and the reverse breakdown voltage was over 350 V.

This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (Vdd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of Vdd above 0.5 V than those of using the control with logic-gate-delay. However, as Vdd is reduced below 0.5 V and gets close to the threshold voltage (Vth) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (Id) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (Id) and Vth of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in Id and Vth is the prerequisite for the SRAM control in the range of Vdd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in Id and Vth for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low Vdd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.

In Japanese, there is frequent alternation between CV morae and moraic geminate consonants. In this study, we analyzed the phonemic environments of consonant gemination (CG) using the "Corpus of Spontaneous Japanese (CSJ)." The results revealed that the environment in which gemination occurs is, to some extent, parallel to that of vowel devoicing. However, there are two crucial differences. One difference is that the CG tends to occur in a /kVk/ environment, whereas such is not the case for vowel devoicing. The second difference is that when the preceding consonant is /r/, gemination occurs, but not vowel devoicing. These observations suggest that the mechanism leading to CG differs from that which leads to vowel devoicing.

This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.

This paper presents an improved architecture of the multistage multibit sigma-delta modulators (ΣΔMs) for wide-band applications. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). Because of in-band zeros introduced by internal loop filters, the proposed architecture enhances the suppression of the in-band quantization noise at a low OSR. The HQCRFF-based modulator with single-bit quantizer has two modes of operation, modulation and oscillation. When the HQCRFF-based modulator is operating in oscillation mode, the feedback path from the quantizer output to the input summing node is disabled and hence the modulator output is free of the quantization noise terms. Although operating in oscillation mode is not allowed for single-stage ΣΔM, the oscillation of HQCRFF-based modulator can improve dynamic range (DR) of the multistage (MASH) ΣΔM. The key to improving DR is to use HQCRFF-based modulator in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. According to theoretical and numerical analysis, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.

A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-µm CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94 ppm/ over the temperature range from -100 to 150 at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.

This paper proposes an improved type of the Hybrid-Parallel Power-Factor-Correction (HP-PFC) converter. It has the advantage of a higher efficiency and improved input current waveform. This advantage achieved through changing new charging path of the bulk capacitor and balancing the power flow from the two transformers to the output. This new circuit has been analyzed using MATLAB/Simulink and confirmed with experiment. As a conclusion, it is confirmed that this improved HP-PFC converter complies with the severe regulation of IEC61000-3-2 Class D. Moreover, a high efficiency of 90% is achieved for 15 V/6 A output power under the worldwide line voltage conditions.

We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.

A new bipolar linear transconductor for low-voltage low-power signal processing is proposed. The proposed circuit has larger input linear range and smaller power dissipation when compared with the conventional bipolar linear transconductor. The experimental results show that the transconductor with a transconductance of 50 µS has a linearity error of less than 0.02% over an input voltage range of 2.1 V at supply voltages of 3 V. The power dissipation of the transconductor is 3.15 mW.

In cellular systems, a code division multiple access (CDMA) technology with array antennas can significantly reduce interferences by taking advantage of the combination of spreading spectrum and spatial filtering. We investigate performance of cellular CDMA systems through adopting two types of array antennas, switched beam forming (SBF) and tracking beam forming (TBF) in the base station. Through Monte-Carlo simulations, we evaluate average bit-error-rate (BER) and outage probability of the systems under log-normal shadowing channels with multi-cell environment. When we consider 2 beams and 4 beams per sector for the SBF method, it is observed that the TBF method gives at least 10% and 30% capacity improvement over the SBF method in aspects of 10-3 BER and 1% outage probability, respectively.

This paper presents a novel ZVS bidirectional 1 kW class DC-DC converter used for a photovoltaic (PV) system. The proposed circuit is based on a boost&buckboost converter, which consists of a boost converter and a buckboost converter. Bidirectional soft switching is realized by using of coupled inductors and auxiliary switches in the circuit. From the analysis of the circuit operation, ZVS conditions of the switches are derived. In the experiment, the maximum efficiency of the proposed converter during forward power flow was 97.1% on output power of 320 W.

This paper presents a novel self-excited ZVS half-bridge converter. This converter including a self-oscillating control circuit is very simply constructed. The converter achieves excellent efficiency, low voltage stress across the switches and low EMI noise by using zero-voltage-switching technique. This converter stores not only magnetic energy in the primary winding of the transformer but also electrostatic energy on the resonant capacitor during the on-periods, so that the converter realizes the miniaturization of the transformer, the reduced conduction losses and the low current stress in the switch. This paper analyzes the behavior of static characteristics by using an extending state-space-averaging method and presents design equations. Based on the analysis, two prototype converters are designed for a 120 W output and a 350 W output. Experimental results are given for two converters and they confirm the validity of the theory. The proposed converters have displayed excellent performance.

This paper presents a novel layout approach using dual supply voltage technique. In Placing and Routing (P&R) phase, conventional approaches for dual supply voltages need to separate low supply voltage cells from high voltage ones. Consequently its layout tends to be complex compared with single supply voltage layout. Our layout approach uses cells having two supply voltage rails. Making these cells is difficult in bulk due to increase in area by n-well isolation or in delay by negative body bias caused by sharing n-well. On the other hand, making cells with two supply voltage rails is easy in body-tied PD-SOI owing to trench isolation of each body of transistor. Since our approach for dual supply voltages offers freedom for placement as much as conventional ones for single supply voltage, exsting P&R tools can be used without special operation. Simulation results with MCNC circuits and adders show that our approach reduces power by 23% and 25%, respectively, showing almost the same delay with single supply voltage layout.

In this paper, a novel type of the step-up high frequency transformer linked full-bridge soft-switching phase-shift PWM DC-DC power converter with ZVS and ZCS bridge legs is proposed for small scale fuel cell power generation systems, automotive AC power supplies. A tapped inductor filter with a freewheeling diode is implemented in the proposed soft-switching DC-DC power converter to minimize the circulating current in the high-frequency step-up transformer primary side and high-frequency inverter stage. Using a tapped inductor filter with a freewheeling diode makes possible to reduce the circulating current without any active switches and theirs gate-drive circuits. The operating principle of the proposed DC-DC power converter with each operation mode during a half cycle of the steady state operation is explained. The optimum design of the tapped inductor turns ratio is described on the basis of the circuit simulation results. Developing 1 kW 100 kHz prototype with power MOSFETs and 36 V DC source verifies the practical effectiveness of the proposed soft-switching DC-DC power converter. The actual efficiency of the proposed DC-DC power converter is obtained 94% for the wide load and output voltage variation ranges.

A stability of the cascade two-stage Power-Factor-Correction converter is investigated. The first stage is boost PFC converter to achieve a near unity power factor and the second stage is forward converter to regulate the output voltage. Previous researches studied the system using linear analysis. However, PFC boost converter is a nonlinear circuit due to the existence of the multiplier and the large variation of the duty cycle. Moreover, the effect of the second stage DC/DC converter on the first stage PFC converter adds more complexity to the nonlinear circuit. In this issue, low-frequency instability has been detected in the two-stage PFC converter assuring the limitation of the prior linear models. Therefore, nonlinear model is proposed to detected and explain these instabilities. The borderlines between stable and unstable operation has been made clear. It is cleared that feedback gains of the first stage PFC and the second stage DC/DC converters are the main affected parts to the total system stability. Then, a simplified nonlinear model is provided. Experiment confirm the two models with a good agreement. These nonlinear models have introduced new PFC design scheme by choosing the minimum required output capacitor and the feedback loop design.

An important issue in applying machine learning algorithms to Natural Language Processing areas such as Named Entity Recognition tasks is to overcome the lack of tagged corpora. Several bootstrapping methods such as co-training have been proposed as a solution. In this paper, we present a different approach using the Web resources. A Named Entity (NE) tagged corpus is generated from the Web using about 3,000 names as seeds. The generated corpus may have a lower quality than the manually tagged corpus but its size can be increased sufficiently. Several features are developed and the decision list is learned using the generated corpus. Our method is verified by comparing it to both the decision list learned on the manual corpus and the DL-CoTrain method. We also present a two-level classification by cascading highly precise lexical patterns and the decision list to improve the performance.