In 3G CDMA mobile communication systems, high data rate services are essential for many key applications. When an MS approaches the cell border, link performance is degraded and more power should be allocated to maintain the link performance. Since the maximum available signal power is limited, the link adaptation mechanism may diminish the data rate to maintain link performance. This implies that the valid coverage shrinks when the data rate increases. The shrinking of valid coverage under a predetermined data rate will strongly impact on the reliability of high data rate services. In this work, the encoded bit error probabilities of 3G CDMA mobile communication systems, over large-scale and large-small-scale fading channels, were analyzed based on SGA and SIGA methods. Analytic methods were also proposed to investigate the issues of coverage shrinking and service data rate variations. Furthermore, the outage probability, cell coverage percentage and the staying probabilities of available data rates were well examined. The proposed analytic methods can be applied, as a preliminary research, to the design of cellular-system-related techniques, such as QoS control, available data rate prediction, power reservation, and service adaptation.

In this paper, authors present new schemes of our proposed Global Open Ethernet (GOE) technology from a viewpoint of improving reliability in metro-area Ethernet environment and show the numerical evidence on their performance results. Although several standardized or vendor proprietary technologies are proposed to improve Ethernet reliability, they still have reliability problems in terms of long failure recovery time (due to forwarding database (FDB) flush and recovery from a root bridge failure on spanning tree protocol), broadcast storm, and packet loss in network reconfiguration. To solve these problems, we introduce three schemes, a Per Destination - Multiple Rapid Spanning Tree Protocol (PD-MRSTP), a GOE Virtual Switch Redundancy Protocol (GVSRP), and an In-Service Reconfiguration (ISR) schemes. PD-MRSTP scheme reduces the failure recovery time by eliminating the need to flush the FDB and to recover from root bridge failures. GVSRP scheme ensures the reliability of connections between a GOE domain and a legacy Ethernet domain. Combined with PD-MRSTP, GVSRP prevents broadcast storm problems due to loops in the inter-domain area. ISR scheme enables in-service bridge replacement and upgrade without packet loss. Evaluating our prototype system, we obtained the following remarkable performance results. The GOE network using PD-MRSTP scheme delivered a fast failure recovery performance (4 ms) independent of the number of MAC address entries, whereas the legacy Ethernet network took 522 ms when a bridge had 6000 MAC address entries. Since we found that the failure recovery time increased in proportion to the number of MAC address entries, the one in large carrier network having one million of MAC address entries would take several tens of seconds. Thus using PD-MRSTP can reduce failure recovery time one ten-thousandth comparing with that of legacy Ethernet. In addition, evaluation of the ISR scheme demonstrated that a network can be upgraded with zero packet loss. Therefore, a GOE-based VPN is a promising alternative to other Ethernet VPNs for its reliability and stability.

In this letter, my proposals for a Floating node voltage-controlled Variable Resistor circuit (FVR) are based upon its advantages as linear and compact. The performance of the proposed circuit was confirmed by PSpice simulation. The simulation results are reported in this letter.

An FRPA (frequency reuse power allocation) technique by employing the frequency reuse notion as a strategy for overcoming the ICI (intercell interference) and maintaining the QoS (quality of service) at the cell boundary is described for broadband cellular networks. In the scheme, the total bandwidth is divided into sub-bands and two different power levels are then allocated to sub-bands based on the frequency reuse for forward-link cell planning. In order to prove the effectiveness of the proposed algorithm, a Monte Carlo simulation was performed based on the Chernoff upper bound. The simulation shows that this technique can achieve a high channel throughput while maintaining the required QoS at the cell boundary.

This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-µm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz-1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.

To achieve both of a high peak performance and low average power characteristics, frequency-voltage cooperative control processor has been proposed. The processor schedules its operating frequency according to the required computation power. Its operating voltage or body bias voltage is adequately modulated simultaneously to effectively cut down either switching current or leakage current, and it results in reduction of total power dissipation of the processor. Since a frequency-voltage cooperative control processor has two or more operating frequencies, there are countless scheduling methods exist to realize a certain number of cycles by deadline time. This proposition is frequently appears in a hard real-time system. This paper proves two important theorems, which give the power-minimum frequency scheduling method for any types of frequency-voltage cooperative control processor, such as Vdd-control type, Vth-control type and Vdd-Vth-control type processors.

A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps: generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullator-norator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullators and norators; and synthesis of the joined-pairs by MOSFETs, and of the current-biases by CMOS current mirrors. It is shown that the proposed synthesis method has the capability to generate already known and new CMOS VF topologies.

A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-µm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.

In this paper, we propose a voltage controlled oscillator (VCO) with up mode type Miller-integrator. The controlled voltage of this VCO can continuously change 0 V center in the positive and negative bidirection. Also, the relationship between control voltage and oscillating frequency shows the good linearity, and the calculated and the measured values agree well.

An efficient pad assignment methodology to minimize voltage drop on a power distribution network is proposed. A combination of successive pad assignment (SPA) with incremental matrix inversion (IMI) determines both location and number of power supply pads to satisfy drop voltage constraint. The SPA creates an equivalent resistance matrix which preserves both pad candidates and power consumption points as external ports so that topological modification due to connection or disconnection between voltage sources and candidate pads is consistently represented. By reusing sub-matrices of the equivalent matrix, the SPA greedily searches the next pad location that minimizes the worst drop voltage. Each time a candidate pad is added, the IMI reduces computational complexity significantly. Experimental results including a 400 pad problem show that the proposed procedures efficiently enumerate pad order in a practical time.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.

To understand the brightness uniformity for the driver of the LED array display, automatic electronic measurement equipment and its testing scheme will be proposed in this paper. The driving performance and dynamic characteristics will be investigated by using the proposed current-based bias voltage regulator. A complete testing procedure will be provided to assess the performance for the LED array display driver.

A CMOS low noise amplifier (LNA) for low-power ultra-wideband (UWB) wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonant frequencies. This work is implemented in 0.18-µm CMOS process and shows a 2.4-9.4-GHz bandwidth. The amplifier provides a maximum forward gain (S21) of 10.9 dB while drawing 7.1 mW from a 1.8-V supply. A noise figure as low as 4.1 dB and an IIP3 of -3.5 dBm have been demonstrated.

A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-µm CMOS process, where the occupied silicon area is only 177 µm106 µm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/ from -10 to 120 without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10 kHz.

A rack-mounted DC power-supply system utilizing Li-ion batteries, which have higher energy density than conventional VRLA batteries, was developed. The system was designed to have the management functions of Li-ion batteries, such as overcharge protection, over-discharge protection, and cell-voltage equalization, by taking operational requirements into consideration. The volume and weight of the entire system were decreased to one-fourth and three-fifths, respectively, of the volume and weight of a conventional system, making the proposed system ideal as a high-energy-density backup power supply. The functions, system configuration, and characteristics of this rack-mounted DC power supply system utilizing Li-ion batteries are described.

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

Multilayered filters with a dielectric distribution along their thickness forming a one-dimensional quasi-fractal structure are theoretically analyzed, focusing on exposing their resonant properties in order to understand a dielectric Menger's sponge resonator [4],[5]. "Quasi-fractal" refers to the triadic Cantor set with finite generation. First, a novel calculation method that has the ability to deal with filters with fine fractal structures is derived. This method takes advantage of Clifford algebra based on the theory of thin-film optics. The method is then applied to classify resonant modes and, especially, to investigate quality factors for them in terms of the following design parameters: a dielectric constant, a loss tangent, and a stage number. The latter determines fractal structure. Finally, behavior of the filters with perfect fractal structure is considered. A crucial finding is that the high quality factor of the modes is not due to the complete self-similarity, but rather to the breaking of such a fractal symmetry.

In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.

OFDM-based networks utilizing the frequency reuse factor of 1 may produce the severe ICI (intercell interference) at the cell boundary even though overall cell capacity is increased and network deployment is facilitated. In the forward-link, the ICI may rise above a QoS (quality of service) threshold beyond some distance from BSs (base stations). In this paper, we analyze the forward-link capacity of an MC-CDMA system as a function of the ICI according to the distance from a cell. To achieve this goal, a closed form of the outage probability is derived and utilized to obtain the accommodated number of users and system parameters.

For a CDMA system with a single carrier, we consider a call control policy at each cell, which gives priority to handoff calls over new calls while meeting the overall call quality. New calls are first under the call control of the threshold type, and then receive services together with the handoff calls but under the outage restriction guaranteeing a pre-specified call quality. An optimization model with such quality-guaranteeing constraints is formulated, which is to determine the threshold value for each cell, minimizing the new call blocking probability. We propose a solution heuristic, with which a number of simulations are conducted under a variety of traffic environments. The computational experiments evaluate the usefulness of our call control scheme in that handoff calls are given an appropriate level of priority while the system capacity is effectively utilized.