In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.

In this paper, we present a discriminative word-character hybrid model for joint Chinese word segmentation and POS tagging. Our word-character hybrid model offers high performance since it can handle both known and unknown words. We describe our strategies that yield good balance for learning the characteristics of known and unknown words and propose an error-driven policy that delivers such balance by acquiring examples of unknown words from particular errors in a training corpus. We describe an efficient framework for training our model based on the Margin Infused Relaxed Algorithm (MIRA), evaluate our approach on the Penn Chinese Treebank, and show that it achieves superior performance compared to the state-of-the-art approaches reported in the literature.

Due to the advancement of software radio and RF technology, cognitive radio(CR) has become an enabling technology to realize dynamic spectrum access through its spectrum sensing and reconfiguration capability. Robust and reliable spectrum sensing is a key factor to discover spectrum opportunity. Single cognitive radios often fail to provide such reliable information because of their inherent sensitivity limitation. Primary signals that are subject to detection by cognitive radios may become weak due to several factors such as fading and shadowing. One approach to overcome this problem is to perform spectrum sensing by using multiple CRs or multiple spectrum sensors. This approach is known as distributed sensing because sensing is carried out through cooperation of spatially distributed sensors. In distributed sensing, sensors should perform spectrum sensing and forward the result to a destination where data fusion is carried out. Depending on the channel conditions between sensors (sensor-to-sensor channel) and between the sensor and the radio (user-channel), we explore different spectrum sensing algorithms where sensors provide the sensing information either cooperatively or independently. Moreover we investigate sensing schemes based on soft information combining (SC), hard information combining (HC). Finally we propose a two-stage detection scheme that uses both SC and HC. The newly proposed detection scheme is shown to provide improved performance compared to sensing based on either HC or SC alone. Computer simulation results are provided to illustrate the performances of the different sensing algorithms.

A voltage-controlled oscillator (VCO) tolerant to process variations at lower supply voltage was proposed. The circuit consists of an on-chip threshold-voltage-monitoring circuit, a current-source circuit, a body- biasing control circuit, and the delay cells of the VCO. Because variations in low-voltage VCO frequency are mainly determined by that of the current in delay cells, a current-compensation technique was adopted by using an on-chip threshold-voltage-monitoring circuit and body-biasing circuit techniques. Monte Carlo SPICE simulations demonstrated that variations in the oscillation frequency by using the proposed techniques were able to be suppressed about 65% at a 1-V supply voltage, compared to frequencies with and without the techniques.

The performance of two-way amplify-and-forward (AF) relay networks is presented. In particular, we derive exact closed-form expressions for symbol error rate (SER), average sum-rate, and outage probability of two-way AF relay systems in independent but not identically distributed (i.n.i.d.) Rayleigh fading channels. Our analysis is validated by a comparison against the results of Monte-Carlo simulations.

This paper presents algorithms for searching text regions with specifying annotated information in tag-annotated text by using Region Algebra. The original algebra and its efficient algorithms are extended to handle both nested regions and crossed regions. The extensions are necessary for text search by using rich linguistic annotations. We first assign a depth number to every nested tag region to order these regions and write efficient algorithms using the depth number for the containment operations which can treat nested tag regions. Next, we introduce variables for attribute values of tags into the algebra to treat annotations in which attributes indicate another tag regions, and propose an efficient method of treating re-entrancy by incrementally determining values for variables. Our algorithms have been implemented in a text search engine for MEDLINE, which is a large textbase of abstracts in medical science. Experiments in tag-annotated MEDLINE abstracts demonstrate the effectiveness of specifying annotations and the efficiency of our algorithms. The system is made publicly accessible at http://www-tsujii.is.s.u-tokyo.ac.jp/medie/.

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead (ILO), and should be considered at both floorplanning and post-floorplanning stages. In this paper, we propose a two phases algorithm framework, called VLSAF, to solve voltage and level shifter assignment problem. At floorplanning phase, we use a convex cost network flow algorithm to assign voltage and a minimum cost flow algorithm to handle level-shifter assignment. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. The experimental results show VLSAF is effective.

This paper presents a wide tuning range VCO with an automatic frequency, gain, and two-step amplitude calibration loop for Digital TV (DTV) tuner applications. To cover the wide tuning range, the fully digital automatic frequency calibration (AFC) loop is used. In addition to the AFC loop, a two-step negative-Gm tuning loop is proposed to provide the optimum negative-Gm to the LC tank in a wide frequency range with a fine resolution. In the coarse negative-Gm tuning loop, the number of active negative-Gm cells is selected digitally based on the target frequency. In the fine negative-Gm tuning loop, the negative-Gm is tuned finely with the bias voltage of the VCO. Also, the digital VCO gain calibration scheme is proposed to compensate for the gain variation in a wide tuning range. The VCO tuning range is 2.6 GHz, from 1.7 GHz to 4.3 GHz, and the power consumption is 2 mA to 4 mA from a 1.8 V supply. The measured VCO phase noise is -120 dBc/Hz at 1 MHz offset.

In this letter, power allocation methods are devised for Amplify-and-Forward (AF) opportunistic relaying systems aiming at minimizing the outage probability. First, we extend the result on outage probability in and develop an approximate expression to simplify the power allocation problem. A corresponding optimization problem is constructed and proved to be convex. Then an iterative numerical method is proposed to find the optimal power allocation factor. We also propose a near-optimal method which can directly calculate the power allocation factor to reduce computational complexity. Numerical results show that the proposed methods have a similar performance with the ideal one, and outperform equal power allocation significantly with little overhead.

A 2.45-GHz-band small passive radio-frequency identification (RFID) tag consists of a small loop antenna and chip, and its size is several millimeters. Because of the tag's poor impedance-matching characteristic and radiation efficiency, an ordinary reader has difficulty reading it. We propose a new technique for reading the tag that involves installing a square half-wavelength meander-line conductor on the reader as an adapter and placing the adapter in the vicinity of the tag, and verify the effectiveness of the technique by simulation and experiment. Moreover, characteristics of simultaneous read of the small RFID tags by the proposed reading technique are revealed by simulation and experimental results.

Recently proposed coded bi-directional relaying protocols increase the spectral efficiency by using network codes, which rely on joint packet encoding and exploitation of previously transmitted and stored information. In this letter, we derive the cumulative density function (CDF) and the probability density function (PDF) of received signal-to-noise ratios (SNRs) for two-phase and three-phase bi-directional coded relaying protocols, respectively, over Rayleigh fading channels. Using these results, we compare the outage performances as well as the average capacities of the protocols. From the numerical observations, we can see that the two-phase protocol has better link-level performances than the three-phase protocol when required data rate is greater than 2 for outate performance and transmit SNR at each node is greater than 18 dB for average capacity, respectively. Otherwise, the three-phase protocol performs better.

To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.

A new on-chip current sensing circuit suitable for step-down switch-mode power converters (SMPC) is presented in this paper. It can be used in a high speed SMPC. The sense voltage is quite accurate and temperature independent. The structure is very simple. Only eight transistors and a sensing resistor are used. This current sensing technique has been fabricated with a standard 0.5 µm DPDM CMOS process. Experimental results show that the proposed circuit can work well in DC-DC converters such that the loading current can be managed through control theories.

The RFID tag system has received attention as an identification source. Each RFID tag is attached to some object. With the unique ID of the RFID tag, a user identifies the object provided with the RFID tag, and derives appropriate information about the object. One of important applications of the RFID technology is the position estimation of RFID tags. It can be very useful to acquire the location information concerning the RFID tags. It can be applied to navigation systems and positional detection systems for robots etc. In this paper, we propose a new position estimation method of RFID tags by using a probabilistic approach. In this method, mobile objects (person and robot, etc.) with RFID readers estimate the positions of RFID tags with multiple communication ranges. We show the effectiveness of the proposed method by computer simulations.

The multiobjective route selection problem (m-RSP) is a key research topic in the car navigation system (CNS) for ITS (Intelligent Transportation System). In this paper, we propose an interactive multistage weight-based Dijkstra genetic algorithm (mwD-GA) to solve it. The purpose of the proposed approach is to create enough Pareto-optimal routes with good distribution for the car driver depending on his/her preference. At the same time, the routes can be recalculated according to the driver's preferences by the multistage framework proposed. In the solution approach proposed, the accurate route searching ability of the Dijkstra algorithm and the exploration ability of the Genetic algorithm (GA) are effectively combined together for solving the m-RSP problems. Solutions provided by the proposed approach are compared with the current research to show the effectiveness and practicability of the solution approach proposed.

The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.

This letter presents a new quadrature voltage-controlled oscillator (QVCO) consisting of two n-core Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The VCOs are used as a single-ended injected injection-locked frequency divider (ILFD). The output of the tail inductor in one ILFD is injected into the injection node in the other ILFD and vice versa. The proposed QVCO has been implemented in the 0.18 µm CMOS technology. At the supply voltage of 1.0 V, the power consumption is 1.8 mW. The free-running frequency is tunable from 4.68 GHz to 5.03 GHz as the tuning voltage is varied from 0.0 V to 1.8 V. The measured phase noise is -113.58 dBc/Hz at the 1 MHz frequency offset from the oscillation frequency of 5.03 GHz and the figure of merit (FOM) of the QVCO is -185.06 dBc/Hz.

In this paper, a low power current protection circuit implemented in a low dropout regulator (LDO) is presented. The proposed circuit, designed in a 0.35 µm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed that the proposed circuit is operable in the regulator output voltage range from VOUT=1.2 V to VOUT=3.6 V and supply voltage range from VDD=VOUT+0.5 V to VDD=5.6 V. Since the proposed circuit is composed of few simple basic circuits such as a comparator and a Schmitt Trigger, it has a low current consumption of less than ISS=0.82 µA at a load current of ILOAD=200 mA. This makes the circuit suitable for low power and low voltage LDO design.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

Using the transient current switch circuit in parallel with the energizing switching contacts for timely control of breaking operation, the increase of contact voltage is suppressed at the last stage of the breaking of electric contacts. Breaking contact voltage Vc and current Ic of electromagnetic relays with Ag contacting electrodes were measured with 12.5-50 V and 0.1-20 A for two hinge springs (Spring constants; 2 N/mm and 0.2 N/mm). The current-decreasing process was clearly measured at the melting voltage Um. After Vc=Um, the breaking time of contact current did not depend on mechanical motion controlled by the two hinge springs and energizing power-supply voltage, but depended on the contact current. The residue of melt electrode was observed optically as a white fusion spot, with radius depending on the energizing current.