This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25 V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional VBE (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified VT (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25 V is required, the voltage gain of the amplifier for VBE becomes less than one, and the voltage gain of the amplifier for VT becomes small. This enables the size of bipolar transistors for VT generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-µm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of 46 ppm/ over 130 change, a line regulation of 2.2 mV/V for the 0.5 V reference voltage with 8.7 µA of current consumption in the voltage reference part, and a 6% change over 130 change for the 13 µA current source.

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

Menger's sponge (MS) is a kind of three-dimensional fractal structure. To analyze non-resonant electromagnetic properties of MS composed of isotropic paraelectric material, a novel, high-speed computation method employing simple recursion equations in terms of scattering amplitudes for two MS's with adjacent stage numbers, which are the parameters describing structural differences of MS's, is formulated. Within the scope of non-resonant electromagnetic phenomena, scattering patterns, forward and backward scattering amplitudes, and total cross sections of MS are investigated as a function of stage number and incident plane waves, and behaviors typical to fractal structures are extracted from the numerical results of the above equations. In addition, scattering properties at infinite stage number are discussed.

A highly accurate measurement method of parameters of MZ-type LN optical intensity modulators is presented. In this method, a CW optical signal is input to an optical terminal and small CW RF signal is applied to an electrode of the modulator. Then sideband levels of an output optical signal at different bias points are measured by using optical spectrum analyzer. By using 1st order sideband levels which are measured at two different bias conditions, and using a compensation method to measured levels, we can obtain accurate chirp parameter even when very small power of RF signal is applied to the modulator. In this method, the chirp parameter can be obtained in good accuracy when the input RF voltage is only 3% of the halfwave voltage.

The cascade of two baseline networks in tandem is a rearrangeable network. The cascade of two omega networks appended with a certain interconnection pattern is also rearrangeable. These belong to the general problem: for what banyan-type network (i.e., bit-permuting unique-routing network) is the tandem cascade a rearrangeable network? We relate the problem to the trace and guide of banyan-type networks. Let τ denote the trace permutation of a 2n2n banyan-type network and γ the guide permutation of it. This paper proves that rearrangeability of the tandem cascade of the network is solely determined by the transposition τγ-1. Such a permutation is said to be tandem rearrangeable when the tandem cascade is indeed rearrangeable. We identify a few tandem rearrangeable permutations, each implying the rearrangeability of the tandem cascade of a wide class of banyan-type networks.

The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.

A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.

This paper presents the design, fabrication and characterization of a low actuation voltage capacitive shunt RF-MEMS switch for microwave and millimeter-wave applications based on a corrugated electrostatic actuated bridge suspended over a concave structure of coplanar waveguide (CPW), with sputtered nickel as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon (HRS) substrate using IC compatible processes for modular integration in a communication devices. The residual stress is very low because having both ends corrugated structure of the bridge in concave structure. The residual stress is calculated about 3-15 MPa in corrugated bridge and 30 MPa in flat bridge. The corrugated bridge of the concave structure requires lower actuation voltages 20-80 V than 50-100 V of the flat bridge of the planar structure in 0.3 to 1.0 µm thick Ni capacitive shunt RF-MEMS switch, in insertion loss 1.0 dB, return loss 12 dB, power loss 10 dB and isolation 28 dB from 0.5 up to 40 GHz. The residual stress of the bridge material and structure is critical to lower the actuation voltage.

Viable techniques such as dynamic voltage scaling (DVS) provide a new design technique to balance system performance and energy saving. In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. We propose an O(nm2) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given set of m real-time tasks running on n identical processors (with or without DVS supports). The same result can be extended to a restricted form of heterogeneous processor model. Meanwhile, we show that on homogeneous processor model more efficient algorithms can be applied and result in time complexity of O(m2) when m ≤ n. For completeness, we also discuss cases without contiguity constraints. We show under such cases the problems become at least as hard as NP-hard.

We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

Cooperative diversity represents an effective way of combating multipath fading through inter-terminal cooperation in wireless networks. In this letter, we propose a new participation strategy that increases the chance of cooperation and present the closed-form expression for outage probability. Numerical results demonstrate that new participation strategy improves the outage performance.

Secret key agreement is a procedure for agreeing on a secret key by exchanging messages over a public channel when a sender, a legitimate receiver (henceforth referred to as a receiver), and an eavesdropper have access to correlated sources. Maurer [6] defined secret key capacity, which is the least upper bound of the key generation rate of the secret key agreement, and presented an upper and a lower bound for the secret key capacity. The advantage distillation capacity is introduced and it is shown that this quantity equals to the secret key capacity. Naive information theoretical expressions of the secret key capacity and the advantage distillation capacity are also presented. An example of correlated sources, for which an analytic expression of the secret key capacity can be obtained, is also presented.

To give comprehensive and consecutive understanding about load line regulation in the previous companion paper [1], more generalized expansion and theoretical derivation will be proposed in this paper. The paper provides an alternative current control approach to control the bias voltage compensation for full-color LED display based on the load-line approach. Modeling and formulation of the driver circuit system will be discussed in detail. Bias voltage compensation based on three load-lines regulation will keep the operating point fixed for the three color cells. Many properties can be observed based on the proposed model. Parasite effect such as the stray resistor and the stray capacitor will be considered in this paper. The associated standard RGB color testing for color cells and white color testing will be illustrated to verify the proposed compensation for the display driver circuit. The objectives of the luminance uniformity and the gray scale control can be achieved by using circuit approach. It is believed that this paper will be helpful to the driver circuit technology for the full-color LED display.

A linear CMOS transconductor is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting to avoid the body effect. To annihilate the non-linear voltage terms, the substrate-bias effect of MOS transistors is treated more accurately in our design. Consequently, the non-linearity of the large-signal transconductance is reduced. The fabricated circuit occupies an area of 245 µm176 µm ( ≈approx 0.043 mm2) and dissipates 0.87 mW from a 3.3 V supply. For an input of 1 Vp-p, the measured output total harmonic distortion is less than 1.2%. The transconductance varies by less than 0.5% in the input range.

In this paper, a multistage parallel interference canceller (MPIC) with multiple-beam reception for a DS-CDMA system is proposed to suppress multiple access interference (MAI) effectively. Its aim is to reduce the computational complexity of the conventional MPIC cascaded with an adaptive array antenna. It employs multiple fixed beams based on phased array and selects suitable beams to demodulate the transmitted signal of each user. Then it suppresses residual interference signals by the MPIC cascaded with multiple-beam receiver. Its bit error rate (BER) performance is evaluated by computer simulations assuming an uplink single-chip-rate multiple-spreading-factor DS-CDMA system over both exponentially decaying 5-path and equal average power 2-path Rayleigh distributed channels. When there are 16 users in an 120-sectored single cell, the proposed receiver with 6-element array antenna and 2-stage MPIC shows better or comparable BER performance compared with that of the conventional receiver. Moreover, the proposed receiver with 8 beams can reduce the number of complex multiplications to about 40% of that of the complexity-reduced conventional receiver over 5-path channels.

Aiming to optimally transmit space-time block codes (STBCs) over distributed antennas (DAs), this paper examines downlink transmit antenna subset selection with power allocation for STBCs in non-ergodic Rayleigh fading channels with receive antenna correlations. Closed-form outage probability is first derived, which is a function of data rate, rate of STBCs, transmit power, large-scale fading (shadowing and path loss), power allocation weights to each DA and receive antenna correlation. However, achieving the optimal power allocation solution is computationally demanding and the use of sub-optimal techniques is necessitated. Assuming feedback of eigenvalues of transmit and receive antenna correlation matrix at the transmitter and accurate channel state information (CSI) at the receiver, an antenna subset selection with sub-optimal power allocation scheme is proposed, whose performance approaches optimal. The effectiveness of this sub-optimal method has been demonstrated by numerical results.

In this letter, a more exact analysis scheme for outage probability is proposed for uplink of direct sequence code division multiple access (DS-CDMA) systems. In the previous works, the effect of call admission control (CAC) on signal to interference ratio (SIR) is considered to evaluate the performance of the outage probability for CDMA systems, however, the effect of CAC on system states is not accurately considered. In this letter, we first analyze the system states more exactly by taking the effect of CAC on CDMA system states into account. Then, the exact probability of the outage is derived according to the exact system states. The probability of the system states and the outage of the proposed approximation scheme are compared with the results of the traditional analysis schemes and the computer simulation. Compared with traditional analysis schemes, the numerical results of the proposed analysis scheme is more close to the computer simulation results.

A multi-stage approach -- which is fast, robust and easy to train -- for a face-detection system is proposed. Motivated by the work of Viola and Jones [1], this approach uses a cascade of classifiers to yield a coarse-to-fine strategy to reduce significantly detection time while maintaining a high detection rate. However, it is distinguished from previous work by two features. First, a new stage has been added to detect face candidate regions more quickly by using a larger window size and larger moving step size. Second, support vector machine (SVM) classifiers are used instead of AdaBoost classifiers in the last stage, and Haar wavelet features selected by the previous stage are reused for the SVM classifiers robustly and efficiently. By combining AdaBoost and SVM classifiers, the final system can achieve both fast and robust detection because most non-face patterns are rejected quickly in earlier layers, while only a small number of promising face patterns are classified robustly in later layers. The proposed multi-stage-based system has been shown to run faster than the original AdaBoost-based system while maintaining comparable accuracy.