This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.

In this paper, we investigate the performance of maximum ratio combining (MRC) in the presence of multiple cochannel interferences over a flat Rayleigh fading channel. Closed-form expressions of signal-to-interference-plus-noise ratio (SINR), outage probability, and average symbol error rate (SER) of quadrature amplitude modulation (QAM) with M-ary signaling are obtained for unequal-power interference-to-noise ratio (INR). We also provide an upper-bound for the average SER using moment generating function (MGF) of the SINR. Moreover, we quantify the array gain loss between pure MRC (MRC system in the absence of CCI) and MRC system in the presence of CCI. Finally, we verify our analytical results by numerical simulations.

Arc discharge generated by breaking electrical contact is considered as a main source of an undesired electromagnetic (EM) noise. To clarify mechanism of generation of the EM noise, feature extraction of bridge and short-time arc waveforms generated by slowly breaking Ag contact was discussed experimentally. The short-duration time arc before the ignition of the continuous metallic arc discharge was observed. The highest probability density voltage is defined as short-arc sustainable voltage (SASV). The relationship between SASV and duration of short-time arc was quantified experimentally. It is revealed that as the arc voltage of the short-time arc is higher, its duration becomes longer.

A fuzzy logic control battery equalizing controller (FLC-BEC) is adopted to control the cell voltage balancing process for a series connected Li-ion battery string. The proposed individual cell equalizer (ICE) is based on the bidirectional Cuk converter operated in the discontinuous capacitor voltage mode (DCVM) to reduce the switching loss and improve equalization efficiency. The ICE with the proposed FLC-BEC can reduce the equalizing time, maintain safe operations during the charge/discharge state and increase the battery string capacity.

The RFID (Radio Frequency IDentification) tag technology is expected as a tool of localization. By the localization of RFID tags, a mobile robot which installs in RFID readers can recognize surrounding environments. In addition, RFID tags can be applied to a navigation system for walkers. In this paper, we propose an adaptive likelihood distribution scheme for the localization of RFID tags. This method adjusts the likelihood distribution depending on the signal intensity from RFID tags. We carry out the performance evaluation of estimated position error by both computer simulations and implemental experiments. We show that the proposed system is more effective than the conventional system.

Open circuit voltage (OCV) of electrical devices is an issue in various fields, whose numerical evaluation needs careful treatment. The open-circuited structure is ill-conditioned because of the singular electric field at the corners, and the TEM component of the electric field has to be extracted before integrated to give the voltage in the direct method of obtaining the OCV. This paper introduces the indirect methods to calculate the OCV, the admittance matrix method and the Norton theorem method. Both methods are based on the short-circuited structure which is well-conditioned. The explicit expressions of the OCV are derived in terms of the admittance matrix elements in the admittance matrix method, and in terms of the short circuit current and the antenna impedance of the electrical device under consideration in the Norton theorem method. These two methods are equivalent in theory, but the admittance matrix method is suitable for the nearby transmitter cases while the Norton theorem method is suitable for the distant transmitter cases. Several examples are given to show the usefulness of the present theory.

Prior studies have shown that the performance of amplify-and-forward (AF) relay systems can be considerably improved by using multiple antennas and low complexity linear processing at the relay nodes. However, there is still a lack of performance analysis for the cases where the processing is based on limited feedback (LFB). Motivated by this, we derive the closed-form expression of the outage probability of AF relay systems with LFB beamforming in this letter. Simulation results are also provided to confirm the analytical studies.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.

Recent advancements in the ubiquitous sensor network field have brought considerable feasibility to the realization of a ubiquitous society. A ubiquitous sensor network will enable the cooperative gathering of environmental information or the detection of special events through a large number of spatially distributed sensor nodes. Thus far, radio frequency identification (RFID) as an application for realizing the ubiquitous environment has mainly been developed for public and industrial systems. To this end, the most existing applications have demanded low-end antennas. In recent years, interests of ubiquitous sensor network have been broadened to medical body area networks (BAN), wireless personal area networks (WPAN), along with ubiquitous smart worlds. This increasing attention toward in ubiquitous sensor network has great implications for antennas. The design of functional antennas has received much attention because they can provide various kinds of properties and operation modes. These high-end antennas have some functions besides radiation. Furthermore, smart sensor nodes equipped with cooperated high-end antennas would allow them to respond adaptively to environmental events. Therefore, some design approaches of functional antennas with sensing and reconfigurability as high-end solution for smart sensor node, as well as low-end antennas for mobile RFID (mRFID) and SAW transponder are presented in this paper.

This paper presents a real-time decision support system (RDSS) based on artificial intelligence (AI) for voltage collapse avoidance (VCA) in power supply networks. The RDSS scheme employs a fuzzy hyperrectangular composite neural network (FHRCNN) to carry out voltage risk identification (VRI). In the event that a threat to the security of the power supply network is detected, an evolutionary programming (EP)-based algorithm is triggered to determine the operational settings required to restore the power supply network to a secure condition. The effectiveness of the RDSS methodology is demonstrated through its application to the American Electric Power Provider System (AEP, 30-bus system) under various heavy load conditions and contingency scenarios. In general, the numerical results confirm the ability of the RDSS scheme to minimize the risk of voltage collapse in power supply networks. In other words, RDSS provides Power Provider Enterprises (PPEs) with a viable tool for performing on-line voltage risk assessment and power system security enhancement functions.

A novel design for temperature-compensated complementary metal-oxide semiconductor (CMOS) voltage reference sources by using the 1st order voltage reference taking into account the electrical property of the conventional current generator was proposed to minimize a temperature coefficient. A temperature coefficient of the proposed voltage reference source was estimated by using the current generator, which operated at smaller or larger temperature in comparison with the optimized operating temperature. The temperature coefficient at temperature range between -40 and 125, obtained from the simulated data by using hynix 0.35 µm CMOS technology, was 3.33 ppm/. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the electrical properties of the conventional current generator can be used to decrease the temperature coefficient.

There are many protocols proposed for protecting Radio Frequency Identification (RFID) system privacy and security. A number of these protocols are designed for protecting long-term security of RFID system using symmetric key or public key cryptosystem. Others are designed for protecting user anonymity and privacy. In practice, the use of RFID technology often has a short lifespan, such as commodity check out, supply chain management and so on. Furthermore, we know that designing a long-term security architecture to protect the security and privacy of RFID tags information requires a thorough consideration from many different aspects. However, any security enhancement on RFID technology will jack up its cost which may be detrimental to its widespread deployment. Due to the severe constraints of RFID tag resources (e.g., power source, computing power, communication bandwidth) and open air communication nature of RFID usage, it is a great challenge to secure a typical RFID system. For example, computational heavy public key and symmetric key cryptography algorithms (e.g., RSA and AES) may not be suitable or over-killed to protect RFID security or privacy. These factors motivate us to research an efficient and cost effective solution for RFID security and privacy protection. In this paper, we propose a new effective generic binary tree based key agreement protocol (called BKAP) and its variations, and show how it can be applied to secure the low cost and resource constraint RFID system. This BKAP is not a general purpose key agreement protocol rather it is a special purpose protocol to protect privacy, un-traceability and anonymity in a single RFID closed system domain.

This paper reports the new gate and recess structure design of millimeter-wave, high power pHEMTs, which highly improves humidity resistance and reliability. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, strong moisture resistance was obtained without degradation of the device characteristics. Moreover, we have designed a stepped recess structure to increase the on-state breakdown voltage without degradation of the power density of the millimeter-wave pHEMT, according to the analysis based on the new nonlinear drain resistance model. Consequently, the developed pHEMT has shown strong humidity resistance with no degradation of the DC characteristics even after 1000 hours storage at 400 K and 85% humidity, and the high on-state breakdown voltage of over 30 V while keeping the high power density of 0.65 W/mm in the Ka band. In addition, the proposed nonlinear drain resistance model effectively explains this power performance.

The multistage Wiener filter (MWF) outperforms the full rank Wiener filter in low sample support environments. However, the MWF adaptive process should be stopped at an optimum stage to get the best performance. There are two methods to stop the MWF adaptive process. One method is to calculate until the final full-stage, and the second method is to terminate at r-stage less than full-stage. The computational load is smaller in the latter method, however, a performance degradation is caused by an additional or subtractive stage calculation. Therefore, it is very important for the r-stage calculation to stop an adaptive process at the optimum stage. In this paper, we propose a simple method based on a cross-correlation coefficient to stop the MWF adaptive process. Because its coefficient is calculated by the MWF forward recursion, the optimum stage is determined automatically and additional calculations are avoided. The performance was evaluated by simulation examples, demonstrating the superiority of the proposed method.

PIN diodes for digital X-ray detection as a single photon counting sensor were fabricated on a floating-zone (FZ) n-type (111), high resistivity (5-10 kΩcm) silicon substrates (500 µm thickness). Its electrical properties such as the leakage current and the breakdown voltage were characterized. The size of pixels was 100 µm100 µm. The p+ guard-ring was formed around the active area to reduce the leakage current. After the p+ active area and guard-ring were fabricated by the ion-implantation, the extrinsic-gettering on the wafer backside was performed to reduce the leakage current by n+ ion-implantation. PECVD oxide was deposited as an IMD layer on front side and then, metal lines were formed on both sides of wafers. The leakage current of detectors was significantly reduced with a guard-ring when compared with that without a guard ring. The leakage current showed the strong dependency on the gap distance between the active area and the guard ring. It was possible to achieve the leakage current lower than 0.2 nA/cm2.

Recently, a method called pipeline stage unification (PSU) has been proposed to reduce energy consumption for mobile processors via inactivating and bypassing some of the pipeline registers and thus adopt shallow pipelines. It is designed to be an energy efficient method especially for the processors under future process technologies. In this paper, we present a mechanism for the PSU controller which can dynamically predict a suitable configuration based on the program phase detection. Our results show that the designed predictor can achieve a PSU degree prediction accuracy of 84.0%, averaged from the SPEC CPU2000 integer benchmarks. With this dynamic control mechanism, we can obtain 11.4% Energy-Delay-Product (EDP) reduction in the processor that adopts a PSU pipeline, compared to the baseline processor, even after the application of complex clock gating.

Aiming at drastically reducing standby leakage current, an SRAM using Four-Terminal- (4T-) FinFETs, named Flex-Vth SRAM, with a dynamic row-by-row threshold voltage control (RRTC) was developed. The Flex-Vth SRAM realizes an extremely low standby-leakage current thanks to the flexible threshold-voltage (Vth) controllability of the 4T-FinFETs, while its access speed and static noise margin (SNM) are maintained. A TCAD-based Monte Carlo simulation indicates that even when the process-induced random variation in the device performance is taken into account, the Flex-Vth SRAM reduces the leakage current to 1/100 of that of a standard SRAM in a 256256 array, where 20-nm-gate-length technologies with the same on-current are assumed.

A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

This work presents an ultra-low-voltage ultra-low-power weak inversion composite MOS transistor. The steady state power consumption and the linear swing signal of the composite transistor are comparable to a single transistor, whereas presenting very high output impedance. This work also presents two interesting applications for the composite transistor; a 1:1 current mirror and an extremely low power temperature sensor, a thermistor. Both implementations are verified in a standard 0.35-µm TSMC CMOS process. The current mirror presents high output impedance, comparable to the cascode configuration, which is highly desirable to improve gain and PSRR of amplifiers circuits, and mirroring relation in current mirrors.

Stochastic approaches for effective power distribution network optimization are proposed. Considering node voltages obtained using dynamic voltage drop analysis as sample variables, multi-variate regression is conducted to optimize clock timing metrics, such as clock skew or jitter. Aggregate correlation coefficient (ACC) which quantifies connectivity between different chip regions is defined in order to find a possible insufficiency in wire connections of a power distribution network. Based on the ACC, we also propose a procedure using linear regression to find the most effective region for improving clock timing metrics. By using the proposed procedure, effective fixing point were obtained two orders faster than by using brute force circuit simulation.