In cellular systems, a code division multiple access (CDMA) technology with array antennas can significantly reduce interferences by taking advantage of the combination of spreading spectrum and spatial filtering. We investigate performance of cellular CDMA systems through adopting two types of array antennas, switched beam forming (SBF) and tracking beam forming (TBF) in the base station. Through Monte-Carlo simulations, we evaluate average bit-error-rate (BER) and outage probability of the systems under log-normal shadowing channels with multi-cell environment. When we consider 2 beams and 4 beams per sector for the SBF method, it is observed that the TBF method gives at least 10% and 30% capacity improvement over the SBF method in aspects of 10-3 BER and 1% outage probability, respectively.

An important issue in applying machine learning algorithms to Natural Language Processing areas such as Named Entity Recognition tasks is to overcome the lack of tagged corpora. Several bootstrapping methods such as co-training have been proposed as a solution. In this paper, we present a different approach using the Web resources. A Named Entity (NE) tagged corpus is generated from the Web using about 3,000 names as seeds. The generated corpus may have a lower quality than the manually tagged corpus but its size can be increased sufficiently. Several features are developed and the decision list is learned using the generated corpus. Our method is verified by comparing it to both the decision list learned on the manual corpus and the DL-CoTrain method. We also present a two-level classification by cascading highly precise lexical patterns and the decision list to improve the performance.

A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.

Reconfigurable logic circuitry has special importance because the popularity of Field Programmable Gate Arrays (FPGA) based applications. A reconfigurable logic based on FGMOS transistors, where a single stage can perform binary operations as well as state machines, is presented. The use of the proposed logic allows the integration of several stages into a single chip because their small area requirement, low voltage and low power characteristics.

This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.

The Flex Power FPGA is presented as a novel FPGA model offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This FPGA model targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. The present paper describes a preliminary simulation study of the Flex Power FPGA. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This FPGA model is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.

Call Admission Control (CAC) is a very important issue in CDMA systems to guarantee a required quality of service (QoS) and to increase system capacity. In this paper, we proposed and analyzed the CAC scheme using multiple criterions (MCAC), which can provide a quicker processing time and better performance. One is based on the number of active users with the minimum/maximum threshold by considering the spillover ratio, and the other is based on the signal to interference ratio (SIR). If active users are lower/higher than the minimum/maximum number of users threshold (N_min )/(N_max ), we accept/reject the new call without any other considerations based on the first criterion. And if the number of active users is between the N_min and N_max, we consider the current SIR to guarantee QoS based on the second criterion. Then the system accepts the new call when the SIR satisfies the system requirements, otherwise, the call is rejected. The multiple criterions scheme is investigated and its performance is compared with the number of user based CAC and power based CAC.

To measure the arc motion in interruption process of low voltage molded case circuit breakers (MCCBs) more precisely, a set of novel 2-D optical fiber system is developed. To improve the spatial resolution of optical fibers, lens with inhomogeneous dielectric is fixed on the top of each fiber. Furthermore, the full hardware control logic facilitates the real-time, synchronous and high-speed processing and breaks through the restricted bus operation frequency range and data stream capacity of microprocessor. The Publisher-Subscribe behavioral design pattern is applied to the software and the loosely coupled relationship between glyph and experimental data is once established, the graphic configuration can be implemented for simulation analysis, and the flexibility and applicability of the whole system are obviously improved. It demonstrates that the system provides a better research technique especially for new generation MCCB with gas driven arc.

In this letter we suggest sets of features to classify genres of web documents. Web documents are different from textual documents in that they contain URL and HTML tags within the pages. We introduce the features specific to web documents, which are extracted from URL and HTML tags. Experimental results enable us to evaluate their characteristics and performances. On the basis of the experimental results, we implement a user interface of a web search engine that presents documents grouped by genres.

A novel high speed, low voltage BiCMOS tristate buffer is presented and its performance characteristics are investigated by using PSPICE simulation. The results obtained are compared with a general CMOS and a couple of previous BiCMOS tristate buffer circuits which are conventional BiCMOS and complementary BiCMOS tristate buffer circuits. It is shown that the proposed BiCMOS tristate buffer circuit outperforms other previous tristate buffer circuits. At lower supply voltage, the proposed circuit has been shown more advantageous speed over previous circuits and it guarantees speed advantage over previous circuits even supply voltage application is at 1.5 volt. The pass transistor technique with a single MOS transistor driving is used to improve the driving capability. Furthermore, a complementary BiCMOS charge pump technique is used to eliminate the voltage loss due to base-emitter turn on voltage and to enhance the driving capability. With the positive and negative charge pump, it can be realized a high speed at low voltage with full swing operation without performance degradation due to shunt CMOS circuit as same as previous complementary BiCMOS tristate buffer circuit.

A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.

Independent shadowing losses are often assumed for computing the frequency reuse distance of cellular mobile communication systems. However, shadowing losses may be partially correlated since the obstacles surrounding a mobile station block similarly the desired signal and interfering signals. We investigate, by computer simulation, how the shadowing correlation impacts the frequency reuse distance of a power controlled cellular system. It is pointed out that the shadowing correlation impacts the frequency reuse distance differently for the uplink and downlink.

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.

In this paper, we proposed a novel two-stage channel estimation (2S-CE) method. In contrast to conventional channel estimation methods, this method makes the maximum use of the information contributed by the known data in every transmission burst. In the first stage, the least-squares (LS) algorithm was used to estimate the channel impulse response (CIR) based on the normal training sequence. Then the maximum channel memory was estimated and used to locate the uncorrupted data in the guard interval. In the second stage, the uncorrupted data together with the normal training sequence were sent to the LS algorithm again to obtain the fine-tuned CIR. To verify the efficiency of the proposed 2S-CE method, both a theoretical analysis and computer simulations have been done. Computer simulation results confirm the analysis results and demonstrate that the proposed 2S-CE method outperforms a conventional single-stage channel estimation method.

This paper presents the improvement of the transient response and stability for a two-stage DC-DC converter by removing the output inductor. The conventional two-stage converter consists of a buck converter used as the first stage and a half-bridge converter used as the second stage. The proposed circuit topology removing the output inductor and the conventional topology are compared. Removing the output inductor results in the system-order reduction of the transfer function. As a result, the stability is improved, and the crossover frequency of the open-loop transfer function becomes higher. The effectiveness of the proposed circuit topology was experimentally confirmed.

A CMOS voltage-to-current converter in weak inversion is presented in this Letter. It can operate for low supply voltage and its power consumption is also low. As the input voltage varies from -0.15 V to 0.15 V, the measured maximum linearity error for the proposed voltage-to-current converter, is about 3.35%. Its power consumption is only 26 µW under the supply voltage of 2 V. The proposed voltage-to-current converter has been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuit is expected to be useful in analog signal processing applications.

A Switched-Opamp is a device in SC circuits for replacing switches with Opamps which operate like a switch. This technique can be acheived in very low voltage operation. In this paper, we present a design for a Switched-Opamp that can operate at a low supply voltage during the ON-phase and can maintain a high output impedance during the OFF-phase.

A low supply voltage CMOS variable-gain low noise amplifier (LNA) is presented in this paper. A folded cascode structure is used to reduce the supply voltage to only 1 V. The conversion gain of the LNA can be controlled by the bias voltage of the connon-gate transistor. When the input signal is weak, the circuit works at high-gain mode to improve the sensitivity. Otherwise, when the input signal is strong, the circuit works at low-gain mode to increase the linearity.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

Uplink synchronous transmission has been proposed to improve the uplink capacity of DS-CDMA systems by means of canceling interference from the main paths of other intra-cell users. A significant capacity gain has been reported in a single cell environment. This Letter further investigates the uplink capacity in a multiple cell environment, where two crucial factors are taken into account, namely code shortage problem and soft handover. The impacts of the target Eb/Io and the other-to-own cell interference ratio, together with the number of channelisation codes, are discussed mathematically and then, confirmed through system level simulations with more realistic parameters.