We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.

Channel errors may exist in Radio Frequency IDentification (RFID) systems due to low power backscattering of tags. These errors prevent the rapid identification of tags, and reducing this deterioration is an important issue. This paper presents performance analysis of various tag anti-collision algorithms and shows that the performances of RFID systems can be improved by applying a proposed robust algorithm in error-prone environments.

In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.

A micro-power active-RFID LSI with an all-digital RF-transmitting scheme achieves experimental 10-m-distance communication with a 1-Mbps data rate in the 300-MHz frequency band. The IC consists of an RF transmitter and a power supply circuit. The RF transmitter generates wireless signals without a crystal. The power supply circuit controls the energy flow from the battery to the IC and offers intermittent operation of the RF transmitter. The IC draws 1.6 µA from a 3.4-V supply and is implemented in a 0.2-µm CMOS process in an area of 1 mm2. The estimated lifetime of the IC is over ten years with a coin-size battery.

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4 V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.

We fabricated metal-oxide-semiconductor (MOS) devices with Pt/Ta2O5 gate stacks and investigated their electrical and structural properties. As increasing RF magnetron sputter-deposition time of Ta2O5 film, the values of equivalent oxide thickness (EOT) and flat band voltage (VFB) increase whilst the density of interfacial trap (Dit) gradually decreases. The effective metal work function (Φm,eff) of Pt metal gate, extracted from the relations of EOT versus VFB are calculated to be ∼5.29 eV, implying that Fermi-level pinning in Ta2O5 gate dielectric is insignificant.

CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

In this letter, a multiuser cooperative network with multiple relays is introduced, and two decode-and-forward (DF) cooperation schemes are proposed aiming at outage-optimal and fair user scheduling, respectively. The outage probability and asymptotic expressions of symbol error probability (SEP) are derived to evaluate these two schemes. Analysis and simulations show that both schemes can achieve full diversity order, which is the combination of cooperative diversity and multiuser diversity.

Power-aware scheduling of periodic tasks in real-time systems has been extensively studied to save energy while still meeting the performance requirement. Many previous studies use the probability information of tasks' execution cycles to assist the scheduling. However, most of these approaches adopt heuristic algorithms to cope with realistic CPU models with discrete frequencies and cannot achieve the globally optimal solution. Sometimes they even show worse results than non-stochastic DVS schemes. This paper presents an optimal DVS scheme for frame-based real-time systems under realistic power models in which the processor provides only a limited number of speeds and no assumption is made on power/frequency relation. A suboptimal DVS scheme is also presented in this paper to work out a solution near enough to the optimal one with only polynomial time expense. Experiment results show that the proposed algorithm can save at most 40% more energy compared with previous ones.

This paper presents a 7 GHz differential current-reused voltage-controlled oscillator (CR-VCO) with low power consumption and low phase noise using 0.18-µm CMOS technology. The output power of this CR-VCO is enhanced by utilizing a trifilar-transformer-feedback technique. The lower phase noise is achieved by the more symmetric voltage swings resulting from the improved balance of switching current. At a 1.5-V DC supply voltage, the power dissipation is only 3.4 mW. The total tuning range is 1.4 GHz (17.9%) as the tuning voltage ranges from 0 V to 1.8 V. The optimum phase noise is around -117.3 dBc/Hz at a frequency offset of 1 MHz from the center frequency of 7.07 GHz. The corresponding output power is around -6.8 dBm. For the proposed CR-VCO, the calculated figures-of-merit, FOM and FOMT , are -188.9 and -193.9 dBc/Hz, respectively.

This paper discusses a dual-stage detection scheme composed of coarse detection stage and refined detection stage for the continuous detection operation of Ultra-Wideband (UWB) detect and avoid (DAA). The threshold factor for the probability of indefinite detection is first proposed and defined to combine the two stages. The proposed scheme focuses on the integration of two different detection schemes with different complexities in order to reduce total computational complexity. A Single-carrier Frequency Division Multiple Access (SC-FDMA) uplink system operating in a Time Division Duplex (TDD) mode is utilized to evaluate the proposed detection scheme. Simulation results indicate that the proposed scheme can make a tradeoff between the detection performance and the computational complexity by setting the probability of indefinite detection.

In this paper, a 0.18-V input three-stage charge pump circuit applying forward body bias is proposed for energy harvesting applications. In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages. By applying the proposed charge pump as the startup in the boost converter, the kick-up input voltage of the boost converter is reduced to 0.18 V. To verify the circuit characteristics, the conventional zero body bias charge pump and the proposed forward body bias charge pump were fabricated with 65 nm CMOS process. The measured output current of the proposed charge pump under 0.18-V input voltage is increased by 170% comparing to the conventional one at the output voltage of 0.5 V. In addition, the boost converter successfully boosts the 0.18-V input to higher than 0.65-V output.

With the emergence of Web 2.0, social tagging systems become highly popular in recent years and thus form the so-called folksonomies. Personalized tag recommendation in social tagging systems is to provide a user with a ranked list of tags for a specific resource that best serves the user's needs. Many existing tag recommendation approaches assume that users are independent and identically distributed. This assumption ignores the social relations between users, which are increasingly popular nowadays. In this paper, we investigate the role of social relations in the task of tag recommendation and propose a personalized collaborative filtering algorithm. In addition to the social annotations made by collaborative users, we inject the social relations between users and the content similarities between resources into a graph representation of folksonomies. To fully explore the structure of this graph, instead of computing similarities between objects using feature vectors, we exploit the method of random-walk computation of similarities, which furthermore enable us to model a user's tag preferences with the similarities between the user and all the tags. We combine both the collaborative information and the tag preferences to recommend personalized tags to users. We conduct experiments on a dataset collected from a real-world system. The results of comparative experiments show that the proposed algorithm outperforms state-of-the-art tag recommendation algorithms in terms of prediction quality measured by precision, recall and NDCG.

This letter introduces a closed form expression for the channel capacity increase achieved by adding a new pair of transmit and receive antennas. By analyzing this expression, an iterative transmit/receive antenna selection algorithm of low computational complexity is proposed. The new algorithm has higher computational complexity than some existing algorithms, but as the results show, the performance improvement of the proposed algorithm approaching more to the optimal algorithm.

AC-waveform synthesis with quantum-mechanical accuracy has been attracting many researchers, especially metrologists in national metrology institutes, not only for its scientific interest but its potential benefit to industries. We describe the current status at National Metrology Institute of Japan of development of a Josephson arbitrary waveform synthesizer based on programmable and pulse-driven Josephson junction arrays.

In this letter, we study the performance of multi-antenna relay networks with limited feedback beamforming in decode-and-forward (DF) relaying. Closed-form expression for both outage probability and symbol error rate are derived by using the moment generation function (MGF) of the combined signal-to-noise ratio (SNR) at the destination. Subjected to a total power constraint, we also explore adaptive power allocation between source and relay to optimize the performance. Simulations are given to verify the correctness of our theoretical derivations. Results show that the proposed adaptive power allocation solution significantly outperforms the uniform power allocation method.

This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.

We propose a distributed data management approach in this paper for a large-scale position-tracking system composed of multiple small systems based on wireless tag technologies such as RFID and Wi-Fi tags. Each of these small systems is called a domain, and a domain server manages the position data of the users belonging to its managing domain and also to the other domains but temporarily residing in its domain. The domain servers collaborate with each other to globally manage the position data, realizing the global position tracking. Several domains can be further grouped to form a larger domain, called a higher-domain, so that the whole system is constructed in a hierarchical structure. We implemented the proposed approach in an experimental environment, and conducted a performance evaluation on the proposed approach and compared it with an existing approach wherein a central server is used to manage the position data of all the users. The results showed that the position data processing load is distributed among the domain servers and the traffic for position data transmission over the backbone network can be significantly restrained.