Chipless RFID tags that use the higher-mode resonances of a transmission line resonator are presented in this paper. We have proposed multimode stepped impedance resonators (SIRs) for this application and reported the fundamental characteristics of an experimental system composed of multimode SIRs with open-circuited ends and a near-field electromagnetic detector using capacitive coupling (electric field) probes for the detector. To improve the frequency response and widen the detection range, we introduced multimode SIRs with short-circuited ends and inductive coupling (magnetic field) probes and measured their properties. To reduce the size of the tag and reader, we examined the frequency responses and found that the optimal configuration consisted of C-shaped tags and detector probes with a spatially orthogonal arrangement. The experimental tag system showed good frequency responses, detection range, and frequency detection accuracy. In particular, the spacing between the tag resonator and the transmission line of the probe, which corresponds to the detection distance, was 5mm or more, and was at least 10 times greater than that of previously reported RFID tag systems using near-field electromagnetic coupling.

In this paper, we investigate a cooperative communication system comprised of a source, a destination, and multiple decode-and-forward (DF) relays in the presence of a potential malicious eavesdropper is within or without the coverage area of the source. Based on the more general Nakagami-m fading channels, we analyze the security performance of the single-relay selection and multi-relay selection schemes for protecting the source against eavesdropping. In the single-relay selection scheme, only the best relay is chosen to assist in the source transmission. Differing from the single-relay selection, multi-relay selection scheme allows multiple relays to forward the source to the destination. We also consider the classic direct transmission as a benchmark scheme to compare with the two relay selection schemes. We derive the exact closed-form expressions of outage probability (OP) and intercept probability (IP) for the direct transmission, the single-relay selection as well as the multi-relay selection scheme over Nakagami-m fading channel when the eavesdropper is within and without the coverage area of the source. Moreover, the security-reliability tradeoff (SRT) of these three schemes are also analyzed. It is verified that the SRT of the multi-relay selection consistently outperforms the single-relay selection, which of both the single-relay and multi-relay selection schemes outperform the direct transmission when the number of relays is large, no matter the eavesdropper is within or without the coverage of the source. In addition, as the number of DF relays increases, the SRT of relay selection schemes improve notably. However, the SRT of both two relay selection approaches become worse when the eavesdropper is within the coverage area of the source.

We report the control of threshold voltage (Vth) for low voltage (5V) operation in OFET by using double gate dielectric layers composed of poly (vinyl cinnamate) and SiO2. We succeeded in realizing a driving voltage of -5V and Vth shift by c.a. 1.0V. And programmed Vth was almost unchanged for 104s, where the relative change of Vth remains more than 99%.

Forward converter is most suitable for low voltage and high current applications such as LEDs, battery chargers, EHV etc. The active clamp transformer reset technique offers many advantages over conventional single-ended reset techniques, including lower voltage stress on the main switch, the ability to switch at zero voltage and duty cycle operation above 50 percent. Several papers have compared the functional merits of the active clamp over the more extensively used RCD clamp, third winding and resonant reset techniques. This paper discusses about a center clamp technique with one common core reset circuit making it suitable for wide input voltage applications with extended duty cycle.

Crack detection is a vital task to maintain a bridge's health and safety condition. Traditional computer-vision based methods easily suffer from disturbance of noise and clutters for a real bridge inspection. To address this limitation, we propose a two-stage crack detection approach based on Convolutional Neural Networks (CNN) in this letter. A predictor of small receptive field is exploited in the first detection stage, while another predictor of large receptive field is used to refine the detection results in the second stage. Benefiting from data fusion of confidence maps produced by both predictors, our method can predict the probability belongs to cracked areas of each pixel accurately. Experimental results show that the proposed method is superior to an up-to-date method on real concrete surface images.

This paper describes a broadband low phase noise VCO implemented in 0.13 µm CMOS process. A 1-bit switched varactor and a 4-bit capacitor array are adopted in cooperation with the automatic frequency calibration (AFC) circuit to lower the VCO tuning gain (KVCO), with a measured AFC time of 6 µs. Several noise reduction techniques are exploited to minimize the phase noise of the VCO. Measurement results show the VCO generates a high frequency range from 11.37 GHz to 14.8 GHz with a KVCO of less than 270 MHz/V. The prototype exhibits a phase noise of -114.6 dBc/Hz @ 1 MHz at 14.67 GHz carrier frequency and draws 10.5 mA current from a 1.2 V supply. The achieved figure-of-merits (FoM=-186.9dBc/Hz, FoMT=-195.3dBc/Hz) favorably compares with the state-of-the-art.

This paper presents a high step-up DC-DC converter for low voltage sources such as solar cells, fuel cells and battery banks. A novel non isolated Zero-Voltage Switching (ZVS) interleaved DC-DC boost converter condition is introduced. In this converter, by using coupled inductor and active clamp circuit, the stored energy in leakage inductor is recycled. Furthermore, ZVS turn on condition for both main and clamp switches are provided. The active clamp circuit suppresses voltage spikes across the main switch and the voltage of clamp capacitor leads to higher voltage gain. In the proposed converter, by applying interleaved technique, input current ripple and also conduction losses are decreased. Also, with simple and effective method without applying any additional element, the input ripple due to couple inductors and active clamp circuit is cancelled to achieve a smooth low ripple input current. In addition, the applied technique in this paper leads to increasing the life cycle of circuit components which makes the proposed converter suitable for high power applications. Finally an experimental prototype of the presented converter with 40 V input voltage, 400 V output voltage and 200 W output power is implemented which verifies the theoretical analysis.

In a large-scale information-sharing platform, such as a cloud storage, it is often required to not only securely protect sensitive information but also recover it in a reliable manner. Public-key encryption with non-interactive opening (PKENO) is considered as a suitable cryptographic tool for this requirement. This primitive is an extension of public-key encryption which enables a receiver to provide a non-interactive proof which confirms that a given ciphertext is decrypted to some public plaintext. In this paper, we present a Tag-KEM/DEM framework for PKENO. In particular, we define a new cryptographic primitive called a Tag-KEM with non-interactive opening (Tag-KEMNO), and prove the KEM/DEM composition theorem for this primitives, which ensures a key encapsulation mechanism (KEM) and a data encapsulation mechanism (DEM) can be, under certain conditions, combined to form a secure PKENO scheme. This theorem provides a secure way of combining a Tag-KEMNO scheme with a DEM scheme to construct a secure PKENO scheme. Using this framework, we explain the essence of existing constructions of PKENO. Furthermore, we present four constructions of Tag-KEMNO, which yields four PKENO constructions. These PKENO constructions coincide with the existing constructions, thereby we explain the essence of these existing constructions. In addition, our Tag-KEMNO framework enables us to expand the plaintext space of a PKENO scheme. Some of the previous PKENO schemes are only able to encrypt a plaintext of restricted length, and there has been no known way to expand this restricted plaintext space to the space of arbitrary-length plaintexts. Using our framework, we can obtain a PKENO scheme with the unbounded-length plaintext space by modifying and adapting such a PKENO scheme with a bounded-length plaintext space.

This letter studies physical-layer security in a cognitive radio (CR) network, where a primary user (PU) is eavesdropped by multiple collusive eavesdroppers. Under the PU secrecy outage constraint to protect the PU, the secondary users (SUs) are assumed to be allowed to transmit. The problem of joint SU scheduling and power control to maximize the SU ergodic transmission rate is investigated for both the scenarios of perfect and imperfect channel state information (CSI). It is shown that, although collusive eavesdroppers degrade the PU performance compared to non-collusive eavesdroppers, the SU performance is actually improved when the number of eavesdroppers is large. It is also shown that our proposed scheme with imperfect CSI can guarantee that the PU performance is unaffected by imperfect CSI.

Once a bug is reported, it is a major concern whether or not the bug is resolved (closed) soon. This paper examines seven metrics quantifying the amount of clues to the early close of reported bugs through a case study. The results show that one of the metrics, the similarity to already-closed bug reports, is strongly related to early-closed bugs.

We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, not only to expand both “write” and “read” stabilities, but also to achieve a low stand-by power and data holding capability in a single low power supply, 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher the word-line voltages for a “read” and “write” operation, respectively. It can also adaptively lower and higher the memory cell supply voltages for the “write” and “hold” operations, and “read” operation, respectively. This paper focuses on the “hold” characteristics and the standby power dissipations (PST) of the developed SRAM. The average PST of the developed SRAM is only 0.984µW, namely, 9.57% of that (10.28µW) of the conventional SRAM at a supply voltage (VDD) of 1.0V. The data hold margin of the developed SRAM is 0.1839V and that of the conventional SRAM is 0.343V at the supply voltage of 1.0V. An area overhead of the SVL circuit is only 1.383% of the conventional SRAM.

To completely utilize the advantages of dynamic voltage and frequency scaling (DVFS) techniques, a quantized decoder (QNT-D) was developed. The QNT-D generates a quantized signal processing quantity (Q) using a predicted signal processing quantity (M). Q is used to produce the optimum frequency (opt.fc) and the optimum supply voltage (opt.VD) that are proportional to Q. To develop a DVFS controlled motion estimation (ME) processor, we used both the QNT-D and a fast ME algorithm called A2BC (Adaptively Assigned Breaking-off Condition) to predict M for each macro-block (MB). A DVFS controlled ME processor was fabricated using 90-nm CMOS technology. The total power dissipation (PT) of the processor was significantly reduced and varied from 38.65 to 99.5 µW, only 3.27 to 8.41 % of PT of a conventional ME processor, depending on the test video picture.

Automatic detection of heart cycle abnormalities in a long duration of ECG data is a crucial technique for diagnosing an early stage of heart diseases. Concretely, Paroxysmal stage of Atrial Fibrillation rhythms (ParAF) must be discriminated from Normal Sinus rhythms (NS). The both of waveforms in ECG data are very similar, and thus it is difficult to completely detect the Paroxysmal stage of Atrial Fibrillation rhythms. Previous studies have tried to solve this issue and some of them achieved the discrimination with a high degree of accuracy. However, the accuracies of them do not reach 100%. In addition, no research has achieved it in a long duration, e.g. 12 hours, of ECG data. In this study, a new mechanism to tackle with these issues is proposed: “Door-to-Door” algorithm is introduced to accurately and quickly detect significant peaks of heart cycle in 12 hours of ECG data and to discriminate obvious ParAF rhythms from NS rhythms. In addition, a quantitative method using Artificial Neural Network (ANN), which discriminates unobvious ParAF rhythms from NS rhythms, is investigated. As the result of Door-to-Door algorithm performance evaluation, it was revealed that Door-to-Door algorithm achieves the accuracy of 100% in detecting the significant peaks of heart cycle in 17 NS ECG data. In addition, it was verified that ANN-based method achieves the accuracy of 100% in discriminating the Paroxysmal stage of 15 Atrial Fibrillation data from 17 NS data. Furthermore, it was confirmed that the computational time to perform the proposed mechanism is less than the half of the previous study. From these achievements, it is concluded that the proposed mechanism can practically be used to diagnose early stage of heart diseases.

An accurate but energy-efficient estimation of a position is important as the number of mobile computing systems grow rapidly. A challenge is to develop a highly accurate but energy efficient estimation method. A particle filter is a key algorithm to estimate and track the position of an object which exhibits non-linear movement behavior. However, it requires high usage of computation resources and energy. In this paper, we propose a scheme which can dynamically adjust the number of particles according to the accuracy of the reference signal for positioning and reduce the energy consumption by 37% on Cortex A7.

Hard-type oscillators for ultrahigh frequency applications were proposed based on resonant tunneling diodes (RTDs) and a HEMT trigger circuit. The hard-type oscillators initiate oscillation only after external excitation. This is advantageous for suppressing the spurious oscillation in the bias line, which is one of the most significant problems in the RTD oscillators. We first investigated a series-connected circuit of a resistor and an RTD for constructing a hard-type oscillator. We carried out circuit simulation using the practical device parameters. It was demonstrated that the stable oscillation can be obtained for such oscillators. Next, we proposed to use series-connected RTDs for the gain block of the hard-type oscillators. The series circuits of RTDs show the negative differential resistance in very narrow regions, or no regions at all, which makes impossible to use such circuits for the conventional soft-type oscillators. However, with the trigger circuit, they can be used for hard-type oscillators. We confirmed the oscillation and the bias stability of these oscillators, and also demonstrated that the voltage swing can be easily increased by increasing the number of RTDs connected in series. This is promising method to overcome the power restriction of the RTD oscillators.

This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.

In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/ under the condition that the temperature range is from -40 to 125 and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

In this paper, we propose a novel phrase-based model for Korean morphological analysis by considering a phrase as the basic processing unit, which generalizes all the other existing processing units. The impetus for using phrases this way is largely motivated by the success of phrase-based statistical machine translation (SMT), which convincingly shows that the larger the processing unit, the better the performance. Experimental results using the SEJONG dataset show that the proposed phrase-based models outperform the morpheme-based models used as baselines. In particular, when combined with the conditional random field (CRF) model, our model leads to statistically significant improvements over the state-of-the-art CRF method.

Cooperative caching is a key technique to reduce rapid growing video-on-demand's traffic by aggregating multiple cache storages. Existing strategies periodically calculate a sub-optimal allocation of the content caches in the network. Although such technique could reduce the generated traffic between servers, it comes with the cost of a large computational overhead. This overhead will be the cause of preventing these caches from following the rapid change in the access pattern. In this paper, we propose a light-weight scheme for cooperative caching by grouping contents and servers with color tags. In our proposal, we associate servers and caches through a color tag, with the aim to increase the effective cache capacity by storing different contents among servers. In addition to the color tags, we propose a novel hybrid caching scheme that divides its storage area into colored LFU (Least Frequently Used) and no-color LRU (Least Recently Used) areas. The colored LFU area stores color-matching contents to increase cache hit rate and no-color LRU area follows rapid changes in access patterns by storing popular contents regardless of their tags. On the top of the proposed architecture, we also present a new routing algorithm that takes benefit of the color tags information to reduce the traffic by fetching cached contents from the nearest server. Evaluation results, using a backbone network topology, showed that our color-tag based caching scheme could achieve a performance close to the sub-optimal one obtained with a genetic algorithm calculation, with only a few seconds of computational overhead. Furthermore, the proposed hybrid caching could limit the degradation of hit rate from 13.9% in conventional non-colored LFU, to only 2.3%, which proves the capability of our scheme to follow rapid insertions of new popular contents. Finally, the color-based routing scheme could reduce the traffic by up to 31.9% when compared with the shortest-path routing.