Fast switching speed, low power consumption, and good stability are some of the important properties of spin transfer torque assisted voltage controlled magnetic anisotropy magnetic tunnel junction (STT-assisted VCMA-MTJ) which makes the non-volatile full adder (NV-FA) based on it attractive for Internet of Things. However, the effects of process variations on the performances of STT-assisted VCMA-MTJ and NV-FA will be more and more obvious with the downscaling of STT-assisted VCMA-MTJ and the improvement of chip integration. In this paper, a more accurate electrical model of STT-assisted VCMA-MTJ is established on the basis of the magnetization dynamics and the process variations in film growth process and etching process. In particular, the write voltage is reduced to 0.7 V as the film thickness is reduced to 0.9 nm. The effects of free layer thickness variation (γtf) and oxide layer thickness variation (γtox) on the state switching as well as the effect of tunnel magnetoresistance ratio variation (β) on the sensing margin (SM) are studied in detail. Considering that the above process variations follow Gaussian distribution, Monte Carlo simulation is used to study the effects of the process variations on the writing and output operations of NV-FA. The result shows that the state of STT-assisted VCMA-MTJ can be switched under -0.3%≤γtf≤6% or -23%≤γtox≤0.2%. SM is reduced by 16.0% with β increases from 0 to 30%. The error rates of writing ‘0’ in the NV-FA can be reduced by increasing Vb1 or increasing positive Vb2. The error rates of writing ‘1’ can be reduced by increasing Vb1 or decreasing negative Vb2. The reduction of the output error rates can be realized effectively by increasing the driving voltage (Vdd).

High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.

For intelligent vision measurement, the geometric image feature extraction is an essential issue. Contour primitive of interest (CPI) means a regular-shaped contour feature lying on a target object, which is widely used for geometric calculation in vision measurement and servoing. To realize that the CPI extraction model can be flexibly applied to different novel objects, the one-shot learning based CPI extraction can be implemented with deep convolutional neural network, by using only one annotated support image to guide the CPI extraction process. In this paper, we propose a multi-stage contour primitives of interest extraction network (MS-CPieNet), which uses the multi-stage strategy to improve the discrimination ability of CPI and complex background. Second, the spatial non-local attention module is utilized to enhance the deep features, by globally fusing the image features with both short and long ranges. Moreover, the dense 4-direction classification is designed to obtain the normal direction of the contour, and the directions can be further used for the contour thinning post-process. The effectiveness of the proposed methods is validated by the experiments with the OCP and ROCM datasets. A 2-D measurement experiments are conducted to demonstrate the convenient application of the proposed MS-CPieNet.

A power-scalable wideband distributed amplifier is proposed. For reducing the power consumption of this power-hungry amplifier, it is efficient to lower the supply voltage. However, there is a hurdle owing to the transistor threshold voltage. In this work, a CMOS deeply depleted channel process is employed to overcome the hurdle.

This brief presents a slope analog-digital converter (ADC)-based supply voltage monitor (SVM) for biofuel-cell-powered supply-sensing systems operating in a supply voltage range of 0.18-0.35V. The proposed SVM is designed to utilize the output of energy harvester extracting power from biological reactions, realizing energy-autonomous sensor interfaces. A burst pulse generator uses a dynamic leakage suppression logic oscillator to generate a stable clock signal under the sub-threshold region for pulse counting. A slope-based voltage-to-time converter is employed to generate a pulse width proportional to the supply voltage with high linearity. The test chip of the proposed SVM is implemented in 180-nm CMOS technology with an active area of 0.018mm2. It consumes 2.1nW at 0.3V and achieves a conversion time of 117-673ms at 0.18-0.35V with a nonlinearity error of -5.5/+8.3mV, achieving an energy-efficient biosensing frontend.

This paper proposes constant voltage design based on K-inverter for cooperative inductive power transfer (IPT) where a nearby receiver picks up power and simultaneously cooperates in relaying the signal toward another distant receiver. In a cooperative IPT system, wireless power is fundamentally transferred to the nearby receiver via one K-inverter and to the distant receiver via two K-inverters. By adding one more K-inverter to the nearby receiver, our design is among the simplest methods as it delivers constant output voltage to each receiver via two K-inverters only. Experimental results verify that the proposed cooperative IPT system can stabilize two output voltages against the load variations while attaining high RF-RF efficiency of 90%.

In response to fast charging systems, Silicon Carbide (SiC) power semiconductor devices are of great interest of the automotive power electronics applications as the next generation of fast charging systems require high voltage batteries. For high voltage battery EVs (Electric Vehicles) over 800V, SiC power semiconductor devices are suitable for 3-phase inverters, battery chargers, and isolated DC-DC converters due to their high voltage rating and high efficiency performance. However, SiC-MOSFETs have two characteristics that interfere with high-speed switching and high efficiency performance operations for SiC MOS-FET applications in automotive power electronics systems. One characteristic is the low voltage rating of the gate-source terminal, and the other is the large internal gate-resistance of SiC MOS-FET. The purpose of this work was to evaluate a proposed hybrid gate drive circuit that could ignore the internal gate-resistance and maintain the gate-source terminal stability of the SiC-MOSFET applications. It has been found that the proposed hybrid gate drive circuit can achieve faster and lower loss switching performance than conventional gate drive circuits by using the current source gate drive characteristics. In addition, the proposed gate drive circuit can use the voltage source gate drive characteristics to protect the gate-source terminals despite the low voltage rating of the SiC MOS-FET gate-source terminals.

Weakly labelled semi-supervised audio tagging (AT) and sound event detection (SED) have become significant in real-world applications. A popular method is teacher-student learning, making student models learn from pseudo-labels generated by teacher models from unlabelled data. To generate high-quality pseudo-labels, we propose a master-teacher-student framework trained with a dual-lead policy. Our experiments illustrate that our model outperforms the state-of-the-art model on both tasks.

Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%.

In the upcoming Internet of Things era, reducing energy consumption of embedded processors is highly desired. Minimum Energy Point Tracking (MEPT) is one of the most efficient methods to reduce both dynamic and static energy consumption of a processor. Previous works proposed a variety of MEPT methods over the past years. However, none of them incorporate their algorithms with practical real-time operating systems, although edge computing applications often require low energy task execution with guaranteeing real-time properties. The difficulty comes from the time complexity for identifying an MEP and changing voltages, which often prevents real-time task scheduling. The conventional Dynamic Voltage and Frequency Scaling (DVFS) only scales the supply voltage. On the other hand, MEPT needs to adjust the body bias voltage in addition. This additional tuning knob makes MEPT much more complicated. This paper proposes an approximate MEPT algorithm, which reduces the complexity of identifying an MEP down to that of DVFS. The key idea is to linearly approximate the relationship between the processor frequency, supply voltage, and body bias voltage. Thanks to the approximation, optimal voltages for a specified clock frequency can be derived immediately. We also propose a task scheduling algorithm, which adjusts processor performance to the workload and then provides a soft real-time capability to the system. The operating system stochastically adjusts the average response time of the processor to be equal to a specified deadline. MEPT will be performed as a general task, and its overhead is considered in the calculation of the frequency. The experiments using a fabricated test chip and on-chip sensors show that the proposed algorithm is a maximum of 16 times more energy-efficient than DVFS. Also, the energy loss induced by the approximation is only 3% at most, and the algorithm does not sacrifice the fundamental real-time properties.

This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload.

We propose a new framework for estimating depth information from a single image. Our framework is relatively small and straightforward by employing a two-stage architecture: a residual network and a simple decoder network. Our residual network in this paper is a remodeled of the original ResNet-50 architecture, which consists of only thirty-eight convolution layers in the residual block following by pair of two up-sampling and layers. While the simple decoder network, stack of five convolution layers, accepts the initial depth to be refined as the final output depth. During training, we monitor the loss behavior and adjust the learning rate hyperparameter in order to improve the performance. Furthermore, instead of using a single common pixel-wise loss, we also compute loss based on gradient-direction, and their structure similarity. This setting in our network can significantly reduce the number of network parameters, and simultaneously get a more accurate image depth map. The performance of our approach has been evaluated by conducting both quantitative and qualitative comparisons with several prior related methods on the publicly NYU and KITTI datasets.

A method for runtime energy optimization based on the supply voltage (Vdd) and the threshold voltage (Vth) scaling is proposed. This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). The MEP dynamically fluctuates depending on the operating conditions determined by a target delay constraint, an activity factor and a chip temperature. In order to track the MEP, this paper proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold region down to the sub-threshold region. Based on the MEP determination formula, an MEP tracking algorithm is also proposed. The MEP tracking algorithm estimates the MEP even though the operating conditions widely change. Measurement results based on a 32-bit RISC processor fabricated in a 65-nm Silicon On Thin Buried oxide (SOTB) process technology show that the proposed method estimates the MEP within a 5% energy loss in comparison with the actual MEP operation.

A temperature-variation-tolerant intermittent startup circuit (ISC) that suppresses quiescent current to 300nA at 0.48V was developed. The ISC is a key circuit for a batteryless wireless sensor that can detect a 1μA generation current of energy harvesting sources from the intervals of wireless signals. The ISC consists of an ultralow-voltage detector composed of a depletion-type MOSFET and low-Vth MOSFETs, a Dickson-type gate-boosted charge pump circuit, and a power-switch control circuit. The detector consists of a voltage reference comparator and a feedback-controlled latch circuit for a hysteresis function. The voltage reference comparator, which has a common source stage with a folded constant-current-source load composed of a depletion-type nMOSFET, makes it possible to reduce the temperature dependency of the detection voltage, while suppressing the quiescent current to 300nA at 0.48V. The ISC fabricated with fully-depleted silicon-on-insulator (FD-SOI) CMOS technology also suppresses the variation of the quiescent current. To verify the effectiveness of the circuit, the ISC was fabricated in a 0.8-μm triple-Vth FD-SOI CMOS process. An experiment on the fabricated system, the ISC boosts the input voltage of 0.48V to 2.4V while suppressing the quiescent current to less than 300nA at 0.48V. The measured temperature coefficient of the detection voltage was ±50ppm/°C. The fluctuation of the quiescent current was 250nA ± 90nA in the temperature range from 0°C to 40°C. An intermittent energy harvesting sensor with the ISC was also fabricated. The sensor could detect a generation current of 1μA at EH sources within an accuracy of ±15% in the temperature range from 0°C to 40°C. It was also successfully applied to a self-powered wireless plant-monitoring sensor system.

This paper presents a conformal retrodirective metagrating with multi-azimuthal-angle operating ability. First, a flat metagrating composed of a periodic array of single rectangular patch elements, two-layer stacked substrates, and a ground plane is implemented to achieve one-directional retroreflection at a specific angle. The elevation angle of the retroreflection is manipulated by precisely tuning the value of the period. To control the energy coupling to the retrodirective mode, the dimensions of the length and width of the rectangular patch are investigated under the effect of changing the substrate thickness. Three values of the length, width, and thickness are then chosen to obtain a high retroreflection power efficiency. Next, to create a conformal design operating simultaneously at multiple azimuthal angles, the rectangular patch array using a flexible ultra-thin guiding layer is conformed to a dielectric cylindrical substrate backed by a perfect electric conductor ground plane. Furthermore, to further optimize the retroreflection efficiency, two circular metallic plates are added at the two ends of the cylindrical substrate to eliminate the specular reflection inside the space of the cylinder. The measured radar cross-section shows a power efficiency of the retrodirective metagrating of approximately 91% and 93% for 30° retrodirected elevation angle at the azimuthal angles of 0° and 90°, respectively, at 5.8GHz.

Air discharge immunity testing for electronic equipment is specified in the standard 61000-4-2 of the International Eelectrotechnical Commission (IEC) under the climatic conditions of temperature (T) from 15 to 35 degrees Celsius and relative humidity (RH) from 30 to 60%. This implies that the air discharge testing is likely to provide significantly different test results due to the wide climatic range. To clarify effects of the above climatic conditions on air discharge testing, we previously measured air discharge currents from an electrostatic discharge (ESD) generator with test voltages from 2kV to 15kV at an approach speed of 80mm/s under 6 combinations of T and RH in the IEC specified range and non-specified climatic range. The result showed that the same absolute humidity (AH), which is determined by T and RH, provides almost the identical waveforms of the discharge currents despite different T and RH, and also that the current peaks at higher test voltages decrease as the AH increases. In this study, we further examine the combined effects of air discharges on test voltages, T, RH and AH with respect to two different approach speeds of 20mm/s and 80mm/s. As a result, the approach speed of 80mm/s is confirmed to provide the same results as the previous ones under the identical climatic conditions, whereas at a test voltage of 15kV under the IEC specified climatic conditions over 30% RH, the 20mm/s approach speed yields current waveforms entirely different from those at 80mm/s despite the same AH, and the peaks are basically unaffected by the AH. Under the IEC non-specified climatic conditions with RH less than 20%, however, the peaks decrease at higher test voltages as the AH increases. These findings obtained imply that under the same AH condition, at 80mm/s the air discharge peak is not almost affected by the RH, while at 20mm/s the lower the RH is, the higher is the peak on air discharge current.

The authors have been investigating the deterioration process of Au-plated slip-ring and Ag-Pd brush system with lubricant to realize stable and long lifetime. Through the past tests, it can be made clear that lubricant is very important for long lifetime, and a simple model of the deterioration process was proposed. However, it is still an issue how the lubricant is deteriorated and also what the relation between lubricant deterioration and contact voltage behavior is. In this paper, the contact voltage waveforms were regularly recorded during the test, and analyzed to obtain the time change of peak voltage and standard deviation during one rotation. Based on these results, it is discussed what happens at the interface between ring and brush with the lubricant. And the following results are made clear. The fluctuation of voltage waveforms, especially peaks of pulse-like fluctuation more easily occurs for minus rings than for plus rings. Further, peak values of the pulse-like fluctuation rapidly decreases and disappear at lower rotation speed as mentioned in the previous works. In addition, each peaks of the pulse-like fluctuation is identified at each position of the ring periphery. From these results, it can be assumed that lubricant film exists between brush and ring surface and electric conduction is realized by tunnel effect. In other words, it can be made clear that the fluctuation would be caused by the lubricant layer, not only by the ring surface. Finally, an electric conduction model is proposed and the above results can be explained by this model.

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.

Vehicle logo detection technology is one of the research directions in the application of intelligent transportation systems. It is an important extension of detection technology based on license plates and motorcycle types. A vehicle logo is characterized by uniqueness, conspicuousness, and diversity. Therefore, thorough research is important in theory and application. Although there are some related works for object detection, most of them cannot achieve real-time detection for different scenes. Meanwhile, some real-time detection methods of single-stage have performed poorly in the object detection of small sizes. In order to solve the problem that the training samples are scarce, our work in this paper is improved by constructing the data of a vehicle logo (VLD-45-S), multi-stage pre-training, multi-scale prediction, feature fusion between deeper with shallow layer, dimension clustering of the bounding box, and multi-scale detection training. On the basis of keeping speed, this article improves the detection precision of the vehicle logo. The generalization of the detection model and anti-interference capability in real scenes are optimized by data enrichment. Experimental results show that the accuracy and speed of the detection algorithm are improved for the object of small sizes.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.