The three-bit balanced ternary quantum voltage generator was designed and tested. This voltage generator is based on zero-crossing Shapiro steps (ZCSSs) in asymmetric two-junction SQUID. ZCSSs were observed on the current-voltage curves, and maximum and minimum current of ZCSSs were almost same, respectively for the three bits. 27-step quantum voltages from -13Φ0f to +13 Φ0f were observed by combinations of inputs of bit1, bit2 and bit3.

The traditional selection cooperation scheme selects the relay with best instantaneous receive signal-to-noise ratio to forward the message and achieves good outage performance, which may however cause poor fairness among relays. In this letter, we propose two practical selection cooperation schemes in Decode-and-Forward (DF) fashion to improve the fairness of relay selection. Numerical results suggest that both of the proposed schemes can achieve fairness close to the strict fairness scheme without outage performance deterioration. It is also validated that these schemes have lower complexities than traditional ones and therefore are practical for real networks.

In this paper, we investigate the outage probability of a dual-hop, channel state information (CSI)-assisted amplify-and-forward (AF) multiple antenna relay network when interference is present at the relay. The source and the destination are equipped with multiple antennas and communicate with each other with the help of a single antenna relay. Transmit antenna selection is performed at the source for source-relay communication. Three receiver combining schemes namely, maximal ratio combining (MRC), equal gain combining (EGC) and selection combining (SC) are considered at the destination. Exact analytical expressions are derived for the outage probability of MRC and SC receiving while an approximate expression is obtained for EGC. Monte-Carlo simulation results are provided to complement analytical results and to demonstrate the effect of interference.

This paper presents a high-efficiency boost converter with voltage clamp function. It clarifies how to design the inductance of the coupled inductor used in the converter, and derives characteristic equations that associate the fluctuation in the input voltage with the output ripple current. For this converter, a theoretical analysis, simulation and experimentation (prototype output: 98 V, 13 A) are performed. As a result, the converter is achieved high efficiency (Maximum efficiency: 98.1%) in the rated output condition, indicating that the voltage stress on the switching power semiconductors can be mitigated by using the voltage clamp function. And it is verified that the snubber circuit can be eliminated in the switching power semiconductors. In addition, the theoretical output ripple current characteristics are corresponded well with simulation and experimental results, and the validity of the design method is proved.

In this paper, we study four simple but fundamental cooperative protocols operating in the decode-and-forward (DF) fashion. Intuitively, finding an appropriate relay for such protocols may greatly improve the outage performance in practice. To this end, we investigate the issue of relay selection in this paper. Specifically, using the asymptotic outage probability, we define and derive the cooperative gain (CG) which quantitatively evaluates the superiority of cooperation over direct transmission. To simplify the process of relay selection, we derive the cooperative region (CR) where a relay is necessarily invoked to aid the communication from source to destination. With the aid of CG and CR, we propose our relay selection algorithm requiring the geographical information rather than the instantaneous channel state information (CSI), and predict the optimal relay locations. In addition, two diversity bounds are also prepared and compared. Finally, both simulations and numerical results are provided on the asymptotic outage probability, CG and CR.

In this letter, we analyze the outage performance of cognitive spectrum sharing in two-way relaying systems. We derive expressions of outage probability for the primary and secondary network over independent but not necessarily identically distributed (i.n.i.d.) Rayleigh fading channels. Monte Carlo simulations are presented to verify the theoretical analyses.

In this letter, non-orthogonal amplify-and-forward (NAF) is considered in a half-duplex two-way system. We derive the closed-form outage probability in the high signal-to-noise ratio (SNR) region, and approximate it with a simpler version to enable power allocation. Then a closed-form power allocation scheme is proposed to improve the outage performance; it uses only statistical channel knowledge (SCK). It is validated that our analyses agree with simulation results and the proposed power allocation approaches the optimal power allocation.

We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.

Dual-vdd has been proposed to optimize the power of circuits without violating the performance. In this paper, different from traditional methods which focus on making full use of slacks of non-critical gates, an efficient min-cut based voltage assignment algorithm concentrating on critical gates is proposed. And then this algorithm is integrated into a searching engine to auto-select rational voltages for dual-vdd system. Experimental results show that our search engine can always achieve good pair of dual-vdd, and our min-cut based algorithm outperformed previous works for voltage assignment both on power consumption and runtime.

This paper introduces novel high-speed and low-power boosted level converters for use in dual-supply systems. The proposed level converters adopt a voltage boosting at the gate of pull-down transistors to improve driving speed and reduce contention problem. Comparison results in a 0.13-µm CMOS process indicated that the proposed level converters provided up to 70% delay reduction with up to 57% power-delay product (PDP) reduction as compared to conventional level converters.

In LDMOS devices for high-voltage applications, there appears a notable fingerprint of current-voltage characteristics known as soft breakdown. Its mechanism is analyzed and modeled on LDMOS devices where a high resistive drift region exists. This analysis has revealed that the softness of breakdown, known as the expansion effect, withholding a run-away of current, is contributed by the flux of holes underneath the gate-overlap region originated by impact-ionization. The mechanism of the expansion effect is modeled and implemented into the compact model HiSIM_HV for circuit simulation. A good agreement between simulated characteristics and 2D-device simulation results is verified.

We derive a closed-form expression for the outage probability (OP), which is an important performance metric used to measure the probability that the target error rate performance of wireless systems exceeds a specified value, of multiple-input multiple-output (MIMO) amplify-and-forward (AF) relaying systems with best antenna selection under independent, but not necessarily identical distributed Nakagami-m fading. To gain further insights on the performance, the asymptotic approximation for OP, which reveals the diversity gain, is presented. We show that the diversity gain is solely determined by the fading severity parameters and increases with number of antennas at all nodes.

An on-chip soft-start circuit based on a switched-capacitor for DC-DC switching regulator is presented. A ramp-voltage, which is generated by a switched-capacitor, is used to make pulse width slowly increase from zero, in order to eliminate the inrush current and the overshoot voltage during start-up. The post simulation results show that the regulator soft starts well with the proposed soft-start circuit.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

Radio frequency identification (RFID) system has gained attention as a new identification source that achieves a ubiquitous environment. Each RFID tag has a unique ID and is attached to an object. A user reads the unique ID of an RFID tag by using RFID readers and obtains the information on the object. One of the important technologies that use the RFID systems is the position estimation of RFID tags. Position estimation means estimating the location of the object with the RFID tag. Acquiring the location information of the RFID tag can be very useful. If a user can know the position of the RFID tag, the position estimation can be applied to a navigation system for walkers. In this paper, we propose a new position estimation method named Swift Communication Range Recognition (S-CRR) as an extended improvement on previous CRR that shortens the estimation delay. In this method, the position of an RFID tag is estimated by selecting the communication area model that corresponds to its boundary angles. We evaluated its performance by experiments and simulations of the RFID system. As the results, we found that S-CRR can estimate the position of an RFID tag comparatively accurately and quickly.

The circuit switching device by the electrical contact needs the high reliability and long lifetime. The very important factor for the high reliability, long lifetime and electromagnetic noise of the electrical contact is to suppress the duration and electromagnetic noise of arc discharge. Usually, the suppression of arc duration method is applying the external magnetic field. But, this method was not able to suppress the metallic arc duration and increased the voltage fluctuation at arc duration. Therefore, the new method for suppressing the duration and noise for electrical contact is expected. In this paper, a new method for suppressing duration and EM noise of arc discharge by applying housing pressure is proposed. To investigate the availability of proposed method, the measurement and some considerations on arc duration, voltage-fluctuation and current noise up to GHz frequency band generated by breaking contact in the applied pressure relay housing are reported. Firstly, voltage waveform and duration of the arc are measured. The effects of the pressure in the relay housing on the duration of the metallic and gaseous phase arcs are discussed. Secondary, voltage fluctuation, the spectrogram of contact voltage and current noise up to GHz frequency band are discussed. In the results, the proposed method with applying pressure makes shorter both durations of metallic and gaseous phases. The shorter duration of metallic phase is an advantage of the proposed method beyond the applying external magnetic field. As the housing pressure is increase, the voltage fluctuation and current noise becomes smalls. The proposed method can suppress the voltage fluctuation as well as arc duration. Consequently, the proposed method is on of the good solution to suppress the duration and electromagnetic noise of the arc discharge from electrical contact and result of this study indicates the basic considerations necessary to ensure good lifetime and EMC designs for electrical contacts.

A low-complexity method for angle estimation in Multiple-input multiple-output radar (MIMO) radar is presented. In this approach, the signal subspace can be spanned by the orthogonal vectors which are obtained by Multi-stage Wiener Filter (MSWF), then the ESPRIT method can be used to estimate direction of departures (DODs) and direction of arrivals (DOAs). Compared with the conventional ESPRIT algorithm, the proposed method does not involve estimation of the covariance matrix and its eigen-decomposition, which alleviates remarkably the computational complexity. Moreover, the proposed method achieves the similar angle estimation performance. Simulation results are presented to verify the efficiency of the proposed method.

Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). However, the identification of control signals for gated registers is hard and designer-intensive work. Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. In this paper, we propose an automatic multi-stage clock gating algorithm with ILP (Integer Linear Programming) formulation, including clock gating control candidate extraction, constraints construction and optimum control signal selection. By multi-stage clock gating, unnecessary clock pulses to clock gating cells can be avoided by other clock gating cells, so that the switching activity of clock gating cells can be reduced. We find that any multi-stage control signals are also single-stage control signals, and any combination of signals can be selected from single-stage candidates. The proposed method can be applied to 3 or more cascaded stages. The multi-stage clock gating optimization problem is formulated as constraints in LP format for the selection of cascaded clock-gating order of multi-stage candidate combinations, and a commercial ILP solver (IBM CPLEX) is applied to obtain the control signals for each register with minimum switching activity. Those signals are used to generate a gate level description with guarded registers from original design, and a commercial synthesis and layout tools are applied to obtain the circuit with multi-stage clock gating. For a set of benchmark circuits and a Low Density Parity Check (LDPC) Decoder (6.6k gates, 212 F.F.s), the proposed method is applied and actual power consumption is estimated using Synopsys NanoSim after layout. On average, 31% actual power reduction has been obtained compared with original designs with structural clock gating, and more than 10% improvement has been achieved for some circuits compared with single-stage optimization method. CPU time for optimum multi-stage control selection is several seconds for up to 25k variables in LP format. By applying the proposed clock gating, area can also be reduced since the multiplexors controlling register inputs are eliminated.

Cooperative relay selection, in which one of multiple relays is selected to retransmit the source signal to the destination, has received considerable attention in recent years, because it is a simple way to obtain cooperative diversity in wireless networks. The exact expression of outage probability for a decode-and-forward cooperative relay selection with multiple source and destination antennas over Rayleigh fading channels was recently derived in [9]. In this letter, we derive the exact expressions of outage probability and diversity-multiplexing tradeoff over independent and non-identically distributed Nakagami-m fading channels as an extension of [9]. We then analyze the effects of various parameters such as fading conditions, number of relays, and number of source and destination antennas on the outage probability.

This paper investigates the effects of n-type doping in the emitter-base heterojunction vicinity on the DC and high-frequency characteristics of InP/InGaAs heterojunction bipolar transistors (HBTs). The n-type doping is shown to be very effective for enhancing the tunneling-injection current from the emitter and thus for reducing the collector-current turn-on voltage. However, it is also revealed that an unnecessary increase in the doping level only degrades the current gain, especially in the low-current region. A higher doping level also increases the emitter junction capacitance. The optimized HBT structures with a 0.5-µm-wide emitter exhibit turn-on voltage as low as 0.78 V and current gain of around 80 at JC = 1 mA/µm2. They also provide a current-gain cutoff frequency, ft, of 280 GHz and a maximum oscillation frequency, fmax, of 385 GHz at VCE = 1 V and JC = 3 mA/µm2. These results indicate that the proposed HBTs are very useful for high-speed and low-power IC applications.