This paper discusses and elaborates an analytical model of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for low-voltage and low-power energy harvesting systems, because the output impedance of the VBC, which is derived from the analytical model, plays an important role in the VBC's performance. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance CF, load capacitance CL, and process dependent parasitic capacitance's parameter k. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful for comparing the relative merits of different types of multi-stage SC VBCs. Moreover, we demonstrate the performance of a prototype SC VBC and energy harvesting system using the SC VBC to show the effectiveness and feasibility of our proposed design guideline.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

This paper describes a method of measuring the unsymmetric voltage of conducted noise using a floating measurement system. Here, floating means that there is no physical connection to the reference ground. The method works by correcting the measured voltage to the desired unsymmetric voltage using the capacitance between the measurement instrument and the reference ground plane acting as the return path of the conducted electromagnetic noise. The existing capacitance measurement instrument needs a probe in contact with the ground, so it is difficult to use for on-site measurement of stray capacitance to ground at troubleshooting sites where the ground plane is not exposed or no ground connection point is available. The authors have developed a method of measuring stray capacitance to ground that does not require physical connection of the probe to the ground plane. The developed method can be used to estimate the capacitance between the measurement instrument and ground plane even if the distance and relative permittivity of the space are unknown. And a method is proposed for correcting the voltage measured with the floating measurement system to obtain the unsymmetric voltage of the noise by using the measured capacitance to ground. In the experiment, the unsymmetric voltage of a sinusoidal wave transmitting on a co-axial cable was measured with a floating oscilloscope in a shield room and the measured voltage was corrected to within 2dB of expected voltage by using the capacitance measured with the developed method. In addition, the voltage of a rectangular wave measured with the floating oscilloscope, which displays sag caused by the stray capacitance to ground, was corrected to a rectangular wave without sag. This means that the phase of the unsymmetric voltage can also be corrected by the measured stray capacitance. From these results, the effectiveness of the proposed methods is shown.

Chipless tag systems composed of multimode stepped impedance resonators (SIRs) and a reader based on near-field electromagnetic coupling have been reported. This resonator structure has advantages including a simple design due to its symmetrical structure and good discrimination accuracy because many higher-order mode resonant frequencies can be used for identification of codes. However, in addition to the disadvantage of long resonator length, the frequency response in the tag system becomes unstable due to deterioration of the isolation between the probes because the same probe structure is used for the excitor and detector. In this paper, we propose two methods to solve these problems. One is to adopt an asymmetrical SIR structure with a short-circuited end and open-circuited end, which reduces the resonator length by half while allowing the same number of codes to be generated. The other is to improve isolation between probes by applying different magnetic field and electric field structures to the two probes for excitation and detection. We also examined assignment and identification conditions and clarified that the available number of codes for a unit tag can be more than 15 bits. It becomes clear that a 75-bit chipless tag on a credit card-sized (55×86mm) printed circuit board can be designed by integrating five unit tags.

Femtocell structures can offer better voice and data exchange in cellular networks. However, interference in such networks poses a major challenge in the practical development of cellular communication. To tackle this issue, an advanced interference mitigation scheme for Line-Of-Sight (LOS) femtocell networks in indoor environments is proposed in this paper. Using a femtocell management system (FMS) that controls all femtocells in a service area, the aggressor femtocells are identified and then the transmitted beam patterns are adjusted using the linear array antenna equipped in each femtocell to mitigate the interference contribution to the neighbouring femtocells. Prior to that, the affected users are switched to the femtocells that provide better throughput levels to avoid increasing the outage probability. This paper considers different femtocell deployment indexes to verify and justifies the feasibility of the findings in different density areas. Relative to fixed and adaptive power control schemes, the proposed scheme achieves approximately 5% spectral efficiency (SE) improvement, about 10% outage probability reduction, and about 7% Mbps average user throughput improvement.

We combine the siamese network and the recurrent regression network, proposing a two-stage tracking framework termed as SiamReg. Our method solves the problem that the classic siamese network can not judge the target size precisely and simplifies the procedures of regression in the training and testing process. We perform experiments on three challenging tracking datasets: VOT2016, OTB100, and VOT2018. The results indicate that, after offline trained, SiamReg can obtain a higher expected average overlap measure.

In this paper, an enhanced well-changed GGNMOS (EW-GGNMOS) is proposed and demonstrated. The new device has the same topology as the conventional 3.3V GGNMOS, except that its well has been changed to the 1.2V p-well. Attributed to higher doping concentration, resulting in a much lower trigger voltage and desirable turn-on uniformity compared to conventional 3.3V GGNMOS. Therefore, we can use EW-GGNMOS as a 3.3V ESD protection device without any additional process.

A fully integrated 16-phase 8-branch Dickson charge pump is proposed and implemented to decrease the power dissipation due to parasitic capacitance at the bottom plate of the boost capacitor. By using the charge recycling concept, 87% of the power consumption related to parasitic capacitance is saved. In a 4-stage version of this charge pump, a maximum power efficiency of 41% is achieved at 35µA output current and 11V output voltage from a 3.3V supply voltage. The proposed multi-branch charge pump can also reach a very low output voltage ripple of only 0.146% at a load resistance of 1MΩ, which is attributed to the fact that the 8-branch charge pump can transfer charges to the output node eight times consecutively during one clock period. In addition, a high voltage gain of 4.6 is achieved in the 4-stage charge pump at light load conditions. The total chip area is 0.57mm2 in a 0.35µm HV CMOS technology.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

In this letter, we adopt two multi-carrier relay selections, i.e., bulk and per-subcarrier (PS), to the multi-hop decode-and-forward relaying orthogonal frequency-division multiplexing with index modulation (OFDM-IM) system. Particularly, in the form of average outage probability (AOP), the influence of joint selection and non-joint selection acting on the last two hops on the system is analyzed. The closed-form expressions of AOPs and the asymptotic AOPs expressions at high signal-to-noise ratio are given and verified by numerical simulations. The results show that both bulk and PS can achieve full diversity order and that PS can provide additional power gain compared to bulk when JS is used. The theoretical analyses in this letter provide an insight into the combination of OFDM-IM and cooperative communication.

In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when VDD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

In video search reranking, in addition to the well-known semantic gap, the intent gap, which is the gap between the representation of the users' demand and the real search intention, is becoming a major problem restricting the improvement of reranking performance. To address this problem, we propose video search reranking based on a semantic representation by multiple tags. In the proposed method, we use relevance feedback, which the user can interact with by specifying some example videos from the initial search results. We apply the relevance feedback to reduce the gap between the real intent of the users and the video search results. In addition, we focus on the fact that multiple tags are used to represent video contents. By vectorizing multiple tags associated with videos on the basis of the Word2Vec algorithm and calculating the centroid of the tag vector as a collective representation, we can evaluate the semantic similarity between videos by using tag features. We conduct experiments on the YouTube-8M dataset, and the results show that our reranking approach is effective and efficient.

In this paper, we investigate a novel joint multi-relay and jammer selection (JMRJS) scheme in order to improve the physical layer security of wireless networks. In the JMRJS scheme, all the relays succeeding in source decoding are selected to assist in the source signal transmission and meanwhile, all the remaining relay nodes are employed to act as friendly jammers to disturb the eavesdroppers by broadcasting artificial noise. Based on the more general Nakagami-m fading channel, we analyze the security performance of the JMRJS scheme for protecting the source signal against eavesdropping. The exact closed-form expressions of outage probability (OP) and intercept probability (IP) for the JMRJS scheme over Nakagami-m fading channel are derived. Moreover, we analyze the security-reliability tradeoff (SRT) of this scheme. Simulation results show that as the number of decode-and-forward (DF)relay nodes increases, the SRT of the JMRJS scheme improves notably. And when the transmit power is below a certain value, the SRT of the JMRJS scheme consistently outperforms the joint single-relay and jammer selection (JSRJS) scheme and joint equal-relay and jammer selection (JERJS) scheme respectively. In addition, the SRT of this scheme is always better than that of the multi-relay selection (MRS) scheme.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

This letter presents the safety confirmation system based on Near Field Communication (NFC) and Ultra High Frequency (UHF) band Radio Frequency IDentification (RFID) tags. Because these RFID tags can operate without the need for internal batteries, the proposed safety confirmation system is effective during large-scale disasters that cause loss of electricity and communication infrastructures. Sharing safety confirmation data between the NFC and UHF band RFID tags was studied to confirm the feasibility of the data sharing. The prototype of the proposed system was fabricated, confirming the feasibility of the proposed safety confirmation system.

Ring voltage-controlled-oscillators (VCOs) are increasingly being used to design ΔΣ ADCs. They have the merits of simple, highly digital and low-voltage tolerant, making them attractive alternatives for the classic scaling-unfriendly operational-amplifier-based methodology. This paper aims to provide a summary on the advancement of VCO-based ΔΣ ADCs. The scope of this paper includes the basics and motivations behind the VCO-based ADCs, followed by a survey covering a wide range of architectures and circuit techniques in both continuous-time (CT) and discrete-time (DT) implementation, and will discuss the key insights behind the contributions and drawbacks of these architectures.

A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.

Adaptive voltage scaling is a promising approach to overcome manufacturing variability, dynamic environmental fluctuation, and aging. This paper focuses on error prediction based adaptive voltage scaling (EP-AVS) and proposes a mean time to failure (MTTF) aware design methodology for EP-AVS circuits. Main contributions of this work include (1) optimization of both voltage-scaled circuit and voltage control logic, and (2) quantitative evaluation of power saving for practically long MTTF. Experimental results show that the proposed EP-AVS design methodology achieves 38.0% power saving while satisfying given target MTTF.

Design of an equivalent slew-rate monolithic pulse generator using bipolar-CMOS-DMOS (BCD) technology for medical ultrasound transmitters is presented in this paper. The pulse generator employs a floating capacitive coupling level-shifter architecture to produce a high-voltage (Vpp=80V) output. The performance of equivalent slew-rate in the rising and falling edge is achieved by carefully choosing the value of coupling capacitors and the size of the final stage high-voltage MOSFETs of the pulse generator. The measured output pulses show the rising and falling time of 8.6nsec and 8.5nsec, respectively with second harmonic distortion down to -40dBc, indicating the designed pulse generator can be used for advanced ultrasonic harmonic imaging systems.

We fabricate and characterize a GaAsSb/InGaAs backward diode (BWD) toward a realization of high sensitivity zero bias microwave rectification for RF wave energy harvest. Lattice-matched p-GaAsSb/n-InGaAs BWDs were fabricated and their current-voltage (I-V) characteristics and S-parameters up to 67 GHz were measured with respect to several sorts of mesa diameters in μm order. Our theoretical model and analysis are well fitted to the measured I-Vs on the basis of WKB approximation of the transmittance. It is confirmed that the interband tunneling due to the heterojunction is a dominant transport mechanism to exhibit the nonlinear I-V around zero bias regime unlike recombination or diffusion current components on p-n junction contribute in large current regime. An equivalent circuit model of the BWD is clarified by confirming theoretical fitting for frequency dependent admittance up to 67 GHz. From the circuit model, eliminating the parasitic inductance component, the frequency dependence of voltage sensitivity of the BWD rectifier is derived with respect to several size of mesa diameter. It quantitatively suggests an effectiveness of mesa size reduction to enhance the intrinsic matched voltage sensitivity with increasing junction resistance and keeping the magnitude of I-V curvature coefficient.