This paper proposes a disaster recovery method for transport networks. In a scenario of recovery from a disaster, a network is repaired through multiple restoration stages because repair resources are limited. In a practical case, a network should provide the reachability of important traffic in transient stages, even as service interruption risks and/or operational overheads caused by transport paths switching are suppressed. Then, we define the multi-objective optimization problem: maximizing the traffic recovery ratio and minimizing the number of switched transport paths at each stage. We formulate our problem as linear programming, and show that it yields pareto-optimal solutions of traffic recovery versus the number of switched paths. We also propose a heuristic algorithm for applying to networks consisting of a few hundred nodes, and show that it can produce sub-optimal solutions that differ only slightly from optimal solutions.

This paper proposes an ultra-low-voltage, wide signal swing, and clock-scalable differential dynamic amplifier using a common-mode voltage detection technique. The essential characteristics of an amplifier, such as gain, linearity, power consumption, noise, etc., are analyzed. In measurement, the proposed dynamic amplifier achieves a 13dB gain with less than 1dB drop over a differential output signal swing of 340mVpp with a supply voltage of 0.5V. The attained maximum operating frequency is 700MHz. With a 0.7V supply, the gain increases to 16dB with a signal swing of 700mVpp. The prototype amplifier is fabricated in 90nm CMOS technology with the low threshold voltage and the deep N-well options.

This paper reports a 65nm 8Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9µs (=0.526MHz) at 0.38V. The operating power is 1.70µW at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.

The outage capacity of the fading cognitive multicast channel (CMC) is investigated in this paper. Assume that the instantaneous channel state information (CSI) of the interference link between the cognitive base station (CBS) and the primary user (PU) is available at the CBS, we derive the outage capacity in Rayleigh fading environments under the interference power and the transmit power constraints. Under the condition that the interference power limit is sufficiently larger or smaller than the transmit power limit, the asymptotic outage capacity is obtained in closed-form. Assume that only the channel distribution information (CDI) of the interference link is available at the CBS, the outage capacity under the interference outage and the transmit power constraints is derived in closed-form. The theoretical results are confirmed by simulations. It is shown that the outage capacity is not degraded due to partial knowledge of the interference link when the interference power limit is sufficiently larger than the transmit power limit. It is also shown that the capacity gain due to increasing the number of the secondary users (SUs) is negligible if the number of the SUs is already large. Additionally, the case of CDI with estimation error is also investigated. Interestingly, we show that the estimation error of CDI may be a positive factor for improving the outage capacity of the CMC.

This paper proposes low-power voltage-mode/current-mode hybrid circuits to realize an arbitrary two-variable logic function and a full-adder function. The voltage and current mode can be selected for low-power operations at low and high frequency, respectively, according to speed requirement. An nMOS pass transistor network is shared to realize voltage switching and current steering for the voltage- and current-mode operations, respectively, which leads to high utilization of the hardware resources. As a result, when the operating frequency is more than 1.15,GHz, the current mode of the hybrid logic circuit is more power-efficient than the voltage mode. Otherwise, the voltage mode is more power-efficient. The power consumption of the hybrid two-variable logic circuit is lower than that of the conventional two-input look-up table (LUT) using CMOS transmission gates, when the operating frequency is more than 800,MHz. The delay and area of the hybrid two-variable logic circuit are increased by only 7% and 13%, respectively

With the development of the Internet, there are more and more shared resources on the Web. Personalized search becomes increasingly important as users demand higher retrieval quality. Personalized search needs to take users' personalized profiles and information needs into consideration. Collaborative tagging (also known as folksonomy) systems allow users to annotate resources with their own tags (features) and thus provide a powerful way for organizing, retrieving and sharing different types of social resources. To capture and understand user preferences, a user is typically modeled as a vector of tag: value pairs (i.e., a tag-based user profile) in collaborative tagging systems. In such a tag-based user profile, a user's preference degree on a group of tags (i.e., a combination of several tags) mainly depends on the preference degree on every individual tag in the group. However, the preference degree on a combination of tags (a tag-group) cannot simply be obtained from linearly combining the preference on each tag. The combination of a user's two favorite tags may not be favorite for the user. In this article, we examine the limitations of previous tag-based personalized search. To overcome their problems, we model a user profile based on combinations of tags (tag-groups) and then apply it to the personalized search. By comparing it with the state-of-the-art methods, experimental results on a real data set shows the effectiveness of our proposed user profile method.

Since electromagnetic (EM) noise resulting from an arc discharge disturbs other electric devices, parameters on electromagnetic compatibility, as well as lifetime and reliability, are important properties for electrical contacts. To clarify the characteristics and the mechanism of the generation of the EM noise, the arc column and voltage fluctuations generated by slowly breaking contacts with external direct current (DC) magnetic field, up to 20,mT, was investigated experimentally using Ag$_{90.7{ m wt%}}$SnO$_{2,9.3{ m wt}%}$ material. Firstly the motion of the arc column is measured by high-speed camera. Secondary, the distribution of the motion of the arc and contact voltage are discussed. It was revealed that the contact voltage fluctuation in the arc duration is related to the arc column motion.

The data rate of VLSI interconnections has been increasing according to the demand for high-speed operation of semiconductors such as CPUs. To realize high performance VLSI systems, high-speed data communication has become an important factor. However, at high-speed data rates, it is difficult to achieve accurate communication without bit errors because of inter-symbol interference (ISI). This paper presents high-speed data communication techniques for VLSI systems using Tomlinson-Harashima Precoding (THP). Since THP can eliminate the ISI with limiting average and peak power of transmitter signaling, THP is suitable for implementing advanced low-voltage VLSI systems. In this paper, 4-PAM (Pulse amplitude modulation) with THP has been employed to achieve high-speed data communication in VLSI systems. Simulation results show that THP can remove the ISI without increasing peak and average power of a transmitter. Moreover, simulation results clarify that multiple-valued data communication is very effective to reduce implementation costs for realizing high-speed serial links.

This study analyzes emotions established between people while interacting in face-to-face conversation. By focusing on empathy and antipathy, especially the process by which they are perceived by external observers, this paper aims to elucidate the tendency of their perception and from it develop a computational model that realizes the automatic inference of perceived empathy/antipathy. This paper makes two main contributions. First, an experiment demonstrates that an observer's perception of an interacting pair is affected by the time lags found in their actions and reactions in facial expressions and by whether their expressions are congruent or not. For example, a congruent but delayed reaction is unlikely to be perceived as empathy. Based on our findings, we propose a probabilistic model that relates the perceived empathy/antipathy of external observers to the actions and reactions of conversation participants. An experiment is conducted on ten conversations performed by 16 women in which the perceptions of nine external observers are gathered. The results demonstrate that timing cues are useful in improving the inference performance, especially for perceived antipathy.

Because dielectrics between active layers have low thermal conductivities, there is a demand to reduce the temperature increase in three-dimensional integrated circuits (3D ICs). This paper demonstrates that, in the design of 3D ICs, different layer assignments often lead to different temperature increases. Based on this observation, we are motivated to perform temperature-aware layer assignment. Our work includes two parts. Firstly, an integer linear programming (ILP) approach that guarantees a minimum temperature increase is proposed. Secondly, a polynomial-time heuristic algorithm that reduces the temperature increase is proposed. Compared with the previous work, which does not take the temperature increase into account, the experimental results show that both our ILP approach and our heuristic algorithm produce a significant reduction in the temperature increase with a very small area overhead.

This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6,Wh (58%) when compared with the conventional method.

A scalable low voltage signaling (SLVS) transmitter, with asymmetric impedance calibration, is proposed for mobile applications which require low power consumption. The voltage swing of the proposed SLVS transmitter is scalable from 40,mV to 440,mV. The proposed asymmetric impedance calibration asymmetrically controls the pull-up and pull-down drivers for the SLVS transmitter with an impedance of 50,$Omega$. This makes it possible to remove the additional regulator used to calibrate the impedance of an output driver by controlling the swing level of a pre-driver. It also maintains the common mode voltage at the center voltage level of the transmitted signal. The proposed SVLS transmitter is implemented using a 0.18-$mu $m 1-poly 6-metal CMOS process with a 1.2-V supply. The active area and power consumption of the transmitter are $250 imes 123 mu$ m$^{2}$ and 2.9,mW/Gb/s, respectively.

Extremely low voltage operation near or below threshold voltage is a key circuit technology to improve the energy efficiency of information systems and to realize ultra-low power sensor nodes. However, it is difficult to operate conventional analog circuits based on amplifier at low voltage. Furthermore, PVT (Process, Voltage and Temperature) variation and random Vth variation degrade the minimum operation voltage and the energy efficiency in both digital and analog circuits. In this paper, extremely low power analog circuits based on comparator and switched capacitor as well as extremely low power digital circuits are presented. Many kinds of circuit technologies are applied to cope with the variation problem. Finally, image processing SoC that integrates digital and analog circuits is presented, where improvement of total performance by a cooperation of analog circuits and digital circuits is demonstrated.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

This paper designs tag antennas to satisfy three key goals: mounting on very small objects, extending the reading range with planar structures, and maintaining stable performance on various materials. First, the size of the tag is reduced up to 17% compared to the half-wavelength dipole without a large reduction in bandwidth and efficiency by introducing an inductively coupled feed structure. Second, the reading range is increased to 1.68 times that of the reference dipole tags while maintaining the planar structure using circular polarization characteristics. Finally, a stable reading range is achieved with a deviation in the reading range of only 30% of that of commercial tags on various objects by employing the capacitively-loaded and T-matching network.

Voltage Regulator Module, called VRM is a dedicated module for supplying power to microprocessor units. Recently, significant improvement of microprocessor units arises new challenges for supplying stable power. For stable and efficient control, multiphase interleaved topology is often used in today's VRM. To achieve high performance VRM, a current sensing circuit with both high efficiency and high accuracy is demanded. To achieve high accuracy, thermal dependency is a problem to be solved. In this paper, a novel alternating voltage controlled current sensing method is proposed for suppressing thermal dependency. In the proposed method, a high frequency AC voltage is superposed on the gate-ON-voltage. Then, the AC channel current is generated, and its amplitude becomes proportional to inductor current. The AC channel current is detected through a LC filter. The proposed current sensing method is very effective for realizing a current mode control DC-DC converter. In first, we simulated the relationship between our proposed current sensing method and a electrical characteristic of a power MOSFET. We used a power MOSFET device model published by a manufacture in this simulation. From the results, we find the gate parasitic capacitance of power MOSFET effects on the sensitivity of the current sensing circuit. Besides, the power dissipation in a power MOSFET increases by the frequency of applied gate ac voltage. Moreover, the proposed current sensing circuit based on the proposed method was designed and simulated the operations by Hspice. From the results, the designed current sensing circuit based on the proposed method has enough wide sensing window from 3A to 30A for VRM applications. Moreover, comparing to the conventional current sensing circuits with the MOSFET ON-resistance, the error of the proposed current sensing circuit can be decreased over 25% near 100°C.

To achieve high quality output speech synthesis systems, data-driven grapheme-to-phoneme (G2P) conversion is usually used to generate the phonetic transcription of out-of-vocabulary (OOV) words. To improve the performance of G2P conversion, this paper deals with the problem of conflicting phonemes, where an input grapheme can, in the same context, produce many possible output phonemes at the same time. To this end, we propose a two-stage neural network-based approach that converts the input text to phoneme sequences in the first stage and then predicts each output phoneme in the second stage using the phonemic information obtained. The first-stage neural network is fundamentally implemented as a many-to-many mapping model for automatic conversion of word to phoneme sequences, while the second stage uses a combination of the obtained phoneme sequences to predict the output phoneme corresponding to each input grapheme in a given word. We evaluate the performance of this approach using the American English words-based pronunciation dictionary known as the auto-aligned CMUDict corpus[1]. In terms of phoneme and word accuracy of the OOV words, on comparison with several proposed baseline approaches, the evaluation results show that our proposed approach improves on the previous one-stage neural network-based approach for G2P conversion. The results of comparison with another existing approach indicate that it provides higher phoneme accuracy but lower word accuracy on a general dataset, and slightly higher phoneme and word accuracy on a selection of words consisting of more than one phoneme conflicts.

In this paper, we consider power allocation over multiple transmit antennas in a distributed transmit antenna system with delay diversity assuming that the power delay profile (PDP) is available for each transmit antenna. This paper demonstrates that the optimal power allocation for outage minimization greatly depends on the system's operating signal-to-noise ratio (SNR) range. With a low operating SNR, it is required to assign all power to the antenna closest to the receiver. On the other hand, when the operating SNR is sufficiently high, power must be allocated proportional to the number of the non-zero elements in the PDP for each antenna.

Filter caches have been studied as an energy efficient solution. They achieve energy savings via selected access to L1 cache, but severely decrease system performance. Therefore, a filter cache system should adopt components that balance execution delay against energy savings. In this letter, we analyze the legacy filter cache system and propose Data Filter Cache with Partial Tag Cache (DFPC) as a new solution. The proposed DFPC scheme reduces energy consumption of L1 data cache and does not impair system performance at all. Simulation results show that DFPC provides the 46.36% energy savings without any performance loss.

This paper gives a write voltage and read reference current generator considering temperature characteristics for multi-level Ge2Sb2Te5-based phase change memories. Since the optimum SET and RESET voltages linearly changes by the temperature, the voltage supply circuit must track this characteristic. In addition, the measurement results show that the read current depends on both read temperature and the write temperature and has exponential dependence on the read temperature. Thus, the binning technique is applied for each read and write temperature regions. The proposed variable TC generator can achieve below ±0.5 LSB precision from the measured differential non-linearity and integral non-linearity. As a result, the temperature characteristics of both the linear write voltage and the exponential read current can be tracked with the proposed variation tolerant linear temperature coefficient current generator.