The influence of the splitter plates on the high-current arc roots formation in low voltage circuit breaker is investigated. One arc quenching chamber model is designed, where the shape of the splitter plates can be changed. The capacitor bank circuit is used to provide the test power supply, and the effective value of the prospective short circuit current is fixed to 10kA. High speed CCD camera is adopted to record the arc images during the arcing duration. Arc current and voltage are also measured to analyze the arc characteristics. In addition, a simplified 1-D thermal-electric model is developed to investigate the influence of the splitter plates on the distribution of the current density of the arc plasma with the assumption of local thermal equilibrium (LTE). It shows that the distance between the arc initial ignition location and the splitter plates is crucial to the arc root formation.

Design equations for satisfying off-nominal operating conditions of the class E amplifier with a nonlinear shunt capacitance for a grading coefficient of 0.5 and the duty cycle D=0.5 are derived. By exploiting the off-nominal class E operation, various amplifier parameters such as input voltage, operating frequency, output power, and load resistance can be set as design specifications. As a result of the analysis in this paper, the following extension of the usability of the class E amplifier was achieved. With rising up the dc supply voltage, the shunt capacitance which achieves the off-nominal operation can be increased. This means that a transistor with higher output capacitance can be used for ZVS operation. This also means that maximum operating frequency which achieves ZVS can be increased. An example of a design procedure of the class E amplifier is given. The theoretical results were verified with an experiment.

This letter investigates the outage performance of a joint transmit and receive antenna selection scheme in an amplify-and-forward two-way relaying system with channel estimation error. A closed-form approximate outage probability expression is derived, based on which the asymptotic outage probability expression is derived to get an insight on system's outage performance at high signal-to-noise (SNR) region. Monte Carlo simulation results are presented to verify the analytical results.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

A 5.6-GHz 1-V balanced LC-tank Colpitts voltage controlled oscillator is designed and implemented with a TSMC 0.18-µm CMOS process. This proposed Colpitts VCO circuit adopts two single-ended complementary LC-tank VCOs coupled by two pairs of varactors. The proposed VCO operates at low power consumption because it has the same dc current path as the np-MOSFETs. The Measured results of the proposed VCO achieve tuning range of 670 MHz from 5.23 to 5.9 GHz while the controlled voltage is tuned from 0 to 1-V, phase noise of -118.8 dBc/Hz at 1 MHz offset frequency from the carrier of 5.6 GHz and output power of -10.97 dBm at the supply voltage of 1 V. The power consumption of the core circuit is 1.79 mW and the chip area including pads is 0.451 (0.55 0.82) mm2.

In this paper, we propose four different strategies of node pair selection in multiple input multiple output (MIMO) interference channel where interference alignment (IA) is considered as a transceiver design method. In the first scheme, we consider the maximization of the sum rate by selecting node pairs in a brute force way. We also propose a sub-optimal sum rate maximization scheme with lower complexity than the first scheme. In the third scheme, we aim to minimize the number of links among pairs which incurs the outage in MIMO interference channel. In the fourth scheme, we suggest a max-min node pair selection scheme to enhance both the sum rate and the outage probability. Simulation results demonstrate that all our proposed node pair selection schemes can increase the sum rate but also while also reducing the outage probability compared to the scheme with random node pair selection.

A modified modeling of residue effect on nano-electro-mechanical nonvolatile memory (NEMory) is presented for considering wet etching process. The effect of a residue under the cantilever is investigated for the optimization. The feasibility of the proposed model is investigated by finite element analysis simulations.

For a development of energy harvesting system, the fact of radio waves and ambient RF (Radio Frequency) sources, including passive devices along with novel circuits, are very closely related to mobile charging devices and energy storage system. The use of schottky diode and voltage multiplier circuits to express on the ambient RF sources surrounding the system is one way that has seen a sudden rise in use for energy harvesting. Practically speaking, the RF and ambient sources can be provided by active and passive devices such as inductors, capacitors, diode, etc. In this paper, we present a schottky based voltage multiplier circuits for mobile charging device which integrate the power generation module with radio wave generation module. We also discuss that multi-stage schematic, e.g., three-stage schottky diode based voltage multiplier circuits, for a continuing effort on energy harvesting system.

Cardinality estimation schemes of Radio Frequency IDentification (RFID) tags using Framed Slotted ALOHA (FSA) based protocol are studied in this paper. Not as same as previous estimation schemes, we consider tag cardinality estimation problem under not only detection errors but also capture effect, where a tag's IDentity (ID) might not be detected even in a singleton slot, while it might be identified even in a collision slot due to the fading of wireless channels. Maximum Likelihood (ML) approach is utilized for the estimation of the detection error probability, the capture effect probability, and the tag cardinality. The performance of the proposed method is evaluated under different system parameters via computer simulations to show the method's effectiveness comparing to other conventional approaches.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail '11' errors and prevent propagation, with measurements in 65 nm CMOS showing seamless operation from 1.6 V to 0.37 V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2 V and 0.4 V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40 nm CMOS measurement results shows correct operation with throughput of 1.2 GHz and 810 MHz at 1.1 V before and after disabling a faulty pipeline stage respectively.

This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140 mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.

This paper is focused on discussing a low-voltage system for lightning, and in particular the testing equipment of surge arresters. Only by demonstrating the performance and applicability of arresters can we seek the most feasible and economic low-voltage solutions. After performing repeated experiments with the same testing samples, using different testing equipment, we compare the different test results in order to select the most suitable and applicable testing equipment. In addition, the basis of a surge current parameter design theory is confirmed and verified through the test results using a simple and compact Impulse Current Generator to test a wide range of samples. By performing the actual analyzes and experiments, we can understand deeply how R, L, and C affect surge current, current wave, and current wave time. The ideal testing equipment standards have been set as follows: (1) Test Voltage up to 20 kV; (2) Expand current range from 1.5 kA to 46.5 kA, with resolution 1.5 kA; and (3) Simple operational procedures.

Spectrum sharing cognitive radio (CR) with maximal ratio combining (MRC) diversity under asymmetric fading is studied. Specifically, the channel on the secondary transmitter (STx) to the secondary receiver (SRx) link is Nakagami-m distributed while the channel on the STx to the primary receiver (PRx) link is Rayleigh distributed, and the channel state information (CSI) on the STx-PRx link is assumed to be outdated due to feedback delay. The outage capacity of the secondary user (SU) is derived under the average interference and peak transmit power constraints. The results supported by simulations are presented and show the effects of various system parameters on the outage capacity. Particularly, it is shown that the outdated CSI has no impact on the outage capacities in the cases of low peak transmit power constraint and zero-outage probability. It is also shown that MRC diversity can significantly improve the outage capacity especially for the zero-outage capacity and the outage capacity under low outage probability.

We have fabricated printed active antenna for flexible information tag which have a loop antenna combined with step-edge vertical channel organic field-effect transistor (SVC-OFET). Fabrication using printing process, characterization of SVC-OFETs, and performances of active antenna elements are discussed in detail.

As an application of low electric field to biomedical engineering, this paper attempts to study the dose-effect of biological effects caused by msPEF with experiments on HeLa cells. MTT assay was used to trace the cell electroporation and examine cell viability. It is observed that with the increasing electric field intensity and pulse numbers, IRE effects will occur successively.