This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm2). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (VDD =0.52 V), the ADPLL only dissipates 269.9 μW at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of -57.3 dBc with the period jitter of 0.217% UI.

Phishing attacks target financial returns by luring Internet users to exposure their sensitive information. Phishing originates from e-mail fraud, and recently it is also spread by social networks and short message service (SMS), which makes phishing become more widespread. Phishing attacks have drawn great attention due to their high volume and causing heavy losses, and many methods have been developed to fight against them. However, most of researches suffered low detection accuracy or high false positive (FP) rate, and phishing attacks are facing the Internet users continuously. In this paper, we are concerned about feature engineering for improving the classification performance on phishing web pages detection. We propose a novel anti-phishing framework that employs feature engineering including feature selection and feature extraction. First, we perform feature selection based on genetic algorithm (GA) to divide features into critical features and non-critical features. Then, the non-critical features are projected to a new feature by implementing feature extraction based on a two-stage projection pursuit (PP) algorithm. Finally, we take the critical features and the new feature as input data to construct the detection model. Our anti-phishing framework does not simply eliminate the non-critical features, but considers utilizing their projection in the process of classification, which is different from literatures. Experimental results show that the proposed framework is effective in detecting phishing web pages.

The threshold voltage variations for actual size MOSFETs obtained by capacitance measurement are compared with those obtained by the current measurement, and their differences are studied for the first time. It is found that the threshold voltage variations obtained by the capacitance measurement show the similar behavior to those current measurement and the absolute value is less than those obtained by the current measurement. The reason for the difference is partially explained by that the local channel dopant non-uniformity along the current path makes the threshold voltage variation obtained from current measurement larger. It is found that the flat-band voltage variations, which are obtained from the measured C-V curves, are small and not significant to the threshold voltage variation.

A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.

In this paper, we investigate the effect of outdated channel state information (CSI) on decode-and-forward opportunistic mobile relaying networks with direct link (DL) between source node and destination node. Relay selection schemes with different levels of CSI are considered: 1) only outdated CSI is available during the relay selection procedure; 2) not only outdated CSI but also second-order statistics information are available in relay selection process. Three relay selection schemes are proposed based on the two levels of outdated CSI. Closed-form expressions of the outage probability are derived for the proposed relay selection schemes. Meanwhile, the asymptotic behavior and the achievable diversity of three relay selection schemes are analyzed. Finally, simulation results are presented to verify our analytical results.

Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

EPCglobal architecture framework is divided into identify, capture, and share layers and defines a collection of standards. It is not fully adequate to build IoT applications because the transducer capability is lacking. IEEE 1451 is a set of standards that defines data exchange format, communication protocols, and various connection interfaces between sensors/actuators and transducer interface modules. By appending IEEE 1451 transducer capability to EPCglobal architecture framework, a consistent EPC scheme expression for heterogeneous things can be achieved at identify layer. It is benefit to extend the upper layers of EPCglobal architecture framework seamlessly. In this paper, we put our emphasis on how to leverage the transducer capability at the capture layer. A device cycle, transducer cycle specification, and transducer cycle report are introduced to collect and process sensor/actuator data. The design and implementation of GS1 EPCglobal Application Level Events (ALE) modules extension are proposed for explaining the design philosophy and verifying the feasibility. It will interact with the capture and query services of EPC Information Services (EPCIS) for IoT applications at the share layer. By cooperating and interacting with these layers of EPCglobal architecture framework, the IoT architecture EPCglobal+ based on international standards is built.

Recent work on joint word segmentation, POS (Part Of Speech) tagging, and dependency parsing in Chinese has two key problems: the first is that word segmentation based on character and dependency parsing based on word were not combined well in the transition-based framework, and the second is that the joint model suffers from the insufficiency of annotated corpus. In order to resolve the first problem, we propose to transform the traditional word-based dependency tree into character-based dependency tree by using the internal structure of words and then propose a novel character-level joint model for the three tasks. In order to resolve the second problem, we propose a novel semi-supervised joint model for exploiting n-gram feature and dependency subtree feature from partially-annotated corpus. Experimental results on the Chinese Treebank show that our joint model achieved 98.31%, 94.84% and 81.71% for Chinese word segmentation, POS tagging, and dependency parsing, respectively. Our model outperforms the pipeline model of the three tasks by 0.92%, 1.77% and 3.95%, respectively. Particularly, the F1 value of word segmentation and POS tagging achieved the best result compared with those reported until now.

An incremental relaying protocol is a promising scheme for preventing the inefficient use of resources in half-duplex cooperative relay networks. In particular, the incremental selection amplify-and-forward (ISAF) relaying scheme is a well-designed protocol under the condition that the source-to-destination (SD) link is static during the two transmission phases. However, from a practical viewpoint, the SD link is not static but varies with time, and thus the ISAF relaying scheme may not work well in the field. In this work, we first show that the outage performance of the ISAF relaying scheme may decrease when the SD link is not static during the two transmission phases. We then propose a modified version of the ISAF relaying scheme which overcomes such a limitation of the ISAF relaying scheme under time-varying environments. Finally, numerical and simulation results are provided to support our findings.

In this paper, we propose a low-power circuit-shared static flip-flop (CS2FF) for extremely low power digital VLSIs. The CS2FF consists of five static NORs and two inverters (INVs). The CS2FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional transmission-gate flip flop (TGFF) used in the most standard cell libraries. SPICE simulations in 0.18-µm standard CMOS process demonstrated that our proposed CS2FF achieved clock-to-Q delay of 18.3ns, setup time of 10.0ns, hold time of 5.5ns, and power dissipation of 9.7nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 16% and power dissipation was reduced by 13% compared with those of conventional TGFF. Measurement results demonstrated that our proposed CS2FF can operate at 0.352V with extremely low energy of 5.93fJ.

In this paper, we analyze a cooperative communication network with multi energy-harvesting and decode-and-forward relays in which the best relay is selected based on criteria such as Maximizing First-Hop Signal to Noise Ratios (SNRs) (MFHS protocol), Maximizing Second-Hop SNRs (MSHS protocol), and Maximizing End-to-End SNRs (MEES protocol). In these protocols, the relays apply power-splitting receivers to harvest energy from radio frequency signals emitted from a source. Thus, each received SNR in the second hop is a function of a direct relay-destination gain and an indirect source-relay gain. The system performance of the proposed protocols is evaluated via exact outage probability analyses and Monte Carlo simulations. For further comparisons, an energy-harvesting decode-and-forward scheme with randomly relay selection (RRS protocol) and an energy-harvesting amplify-and-forward scheme (BAF protocol) are investigated and discussed. The simulation results show that 1) the MEES protocol outperforms the MFHS and MSHS protocols, and the MFHS protocol is more efficient than the MSHS protocol in the low SNR regions; 2) the proposed protocols achieve the best performance at the specific optimal power splitting ratios for which the MEES protocol has a balanced ratio for energy harvesting and decoding capacity; and 3) the theoretical analyses agree well with the simulation results.

This paper addresses the problem of job scheduling in volunteer computing (VC) systems where each computation job is replicated and allocated to multiple participants (workers) to remove incorrect results by a voting mechanism. In the job scheduling of VC, the number of workers to complete a job is an important factor for the system performance; however, it cannot be fixed because some of the workers may secede in real VC. This is the problem that existing methods have not considered in the job scheduling. We propose a dynamic job scheduling method which considers the expected probability of completion (EPC) for each job based on the probability of worker's secession. The key idea of the proposed method is to allocate jobs so that EPC is always greater than a specified value (SPC). By setting SPC as a reasonable value, the proposed method enables to complete jobs without excess allocation, which leads to the higher performance of VC systems. We assume in this paper that worker's secession probability follows Weibull-distribution which is known to reflect more practical situation. We derive parameters for the distribution using actual trace data and compare the performance of the proposed and the previous method under the Weibull-distribution model, as well as the previous constant probability model. Simulation results show that the performance of the proposed method is up to 5 times higher than that of the existing method especially when the time for completing jobs is restricted, while keeping the error rate lower than a required value.

This paper analyzes the impact of directional antennas in improving the transmission capacity, defined as the maximum allowable spatial node density of successful transmissions multiplied by their data rate with a given outage constraint, in wireless networks. We consider the case where the gain Gm for the mainlobe of beamwidth can scale at an arbitrarily large rate. Under the beamwidth scaling model, the transmission capacity is analyzed for all path-loss attenuation regimes for the following two network configurations. In dense networks, in which the spatial node density increases with the antenna gain Gm, the transmission capacity scales as Gm4/α, where α denotes the path-loss exponent. On the other hand, in extended networks of fixed node density, the transmission capacity scales logarithmically in Gm. For comparison, we also show an ideal antenna model where there is no sidelobe beam. In addition, computer simulations are performed, which show trends consistent with our analytical behaviors. Our analysis sheds light on a new understanding of the fundamental limit of outage-constrained ad hoc networks operating in the directional mode.

In this paper, a new single soft switched forward converter with a self driven synchronous rectification (SDSR) is introduced. In the proposed converter, a soft switching condition (ZCS turn on and ZVS turn off) is provided for the switch, by an auxiliary circuit without any extra switch. In additional, this auxiliary circuit does not impose high voltage or current stresses on the converter. Since the proposed converter uses SDSR to reduce conductive loss of output rectifier, the rectifier switches are switched under soft switching condition. So, the conductive and switching losses on the converter reduce considerably. Also, implementing control circuit of this converter is very simple, due to the self-driven method employed in driving synchronous rectification and the converter is controlled by pulse width modulation (PWM). The experimental results of the proposed converter are presented to confirm the theoretical analysis.

The effect of annealing on the field emission characteristics of a field emitter comprising diamond micropowder was investigated. The threshold voltage Vth at which the emission current begins to flow decreased as the annealing temperature increased, and a minimum Vth was obtained at an annealing temperature of 1345K. The reduction in threshold voltage was due to a reduction in the work function with annealing.

The problem of power allocation for the secondary user (SU) in a cognitive radio (CR) network is investigated in this paper. The primary user (PU) is protected by the average interference power constraint. Besides the average interference power constraint at the PU, the transmit power of the SU is also subject to the peak or average transmit power constraint. The aim is to balance between the goal of maximizing the ergodic capacity and the goal of minimizing the outage probability of the SU. Power allocation schemes are then proposed under the aforementioned setups. It is shown that the proposed power allocation schemes can achieve high ergodic capacity while maintaining low outage probability, whereas existing schemes achieve either high ergodic capacity with high outage probability or low outage probability with low ergodic capacity.

We propose a joint channel, power and rate allocation scheme to minimize the weighted group outage probability of the secondary users (SUs) in a downlink cognitive radio (CR) multicast network coexisting with a primary network, subject to the service outage constraint as well as the interference power constraint and the transmit power constraint. It is validated by simulation results that, compared to the existing schemes, the proposed scheme achieves lower group outage probability.

In this study, we propose a two-step approach to evaluate electromagnetic interference (EMI) with a wearable vital signal sensor. The two-step approach combines a quasi-static electromagnetic (EM) field analysis and an electric circuit analysis, and is applied to the EMI evaluation at frequencies below 1 MHz for our developed wearable electrocardiogram (ECG) to demonstrate its usefulness. The quasi-static EM field analysis gives the common mode voltage coupled from the incident EM field at the ECG sensing electrodes, and the electric circuit analysis quantifies a differential mode voltage at the differential amplifier output of the ECG detection circuit. The differential mode voltage has been shown to come from a conversion from the common mode voltage due to an imbalance between the contact impedances of the two sensing electrodes. When the contact impedance is resistive, the induced differential mode voltage increases with frequency up to 100kHz, and keeps constant after 100kHz, i.e., exhibits a high pass filter characteristic. While when the contact impedance is capacitive, the differential mode voltage exhibits a band pass filter characteristic with the maximum at frequency of around 150kHz. The differential voltage may achieve nearly 1V at the differential amplifier output for an imbalance of 30% under 10V/m plane-wave incident electric field, and completely mask the ECG signal. It is essential to reduce the imbalance as much as possible so as to prevent a significant interference voltage in the amplified ECG signal.