Scaling the supply voltage (Vdd) and threshold voltage (Vth) for minimizing the energy consumption of processors dynamically is highly desired for applications such as wireless sensor network and Internet of Things (IoT). In this paper, we refer to the pair of Vdd and Vth, which minimizes the energy consumption of the processor under a given operating condition, as a minimum energy point (MEP in short). Since the MEP is heavily dependent on an operating condition determined by a chip temperature, an activity factor, a process variation, and a performance required for the processor, it is not very easy to closely track the MEP at runtime. This paper proposes a simple but effective algorithm for dynamically tracking the MEP of a processor under a wide range of operating conditions. Gate-level simulation of a 32-bit RISC processor in a 65nm process demonstrates that the proposed algorithm tracks the MEP under a situation that operating condition widely vary.

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Capability of SOTB to effectively reduce leakage by body biasing is fully exploited in BBS. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

Hotspots occur frequently in 3D multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. We present a new thermally constrained task scheduler based on a thermal-pattern-aware voltage assignment (TPAVA) to reduce hotspots in and optimize the performance of 3D-MCPs. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different initial operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. The proposed task scheduler consists of an on-line allocation strategy and a new voltage-scaling strategy. In particular, the proposed on-line allocation strategy uses the temperature-variation rates of the cores and takes into two important thermal behaviors of 3D-MCPs that can effectively minimize occurrences of hotspots in both thermally homogeneous and heterogeneous 3D-MCPs. Furthermore, a new vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs is used to handle thermal emergencies. Experimental results indicate that, when compared to a previous online thermally constrained task scheduler, the proposed task scheduler can reduce hotspot occurrences by approximately 66% (71%) and improve throughput by approximately 8% (2%) in thermally homogeneous (heterogeneous) 3D-MCPs. These results indicate that the proposed task scheduler is an effective technique for suppressing hotspot occurrences and optimizing throughput for 3D-MCPs subject to thermal constraints.

Scaling supply voltage (VDD) and threshold voltage (Vth) dynamically has a strong impact on energy efficiency of CMOS LSI circuits. Techniques for optimizing VDD and Vth simultaneously under dynamic workloads are thus widely investigated over the past 15 years. In this paper, we refer to the optimum pair of VDD and Vth, which minimizes the energy consumption of a circuit under a specific performance constraint, as a minimum energy point (MEP). Based on the simple transregional models of a CMOS circuit, this paper derives a simple necessary and sufficient condition for the MEP operation. The simple condition helps find the MEP of CMOS circuits. Measurement results using standard-cell based memories (SCMs) fabricated in a 65-nm process technology also validate the condition derived in this paper.

In this letter, we consider a cognitive radio network where multiple secondary users (SUs) share the spectrum bands with multiple primary users (PUs) who are facing security threats from multiple eavesdroppers. By adopting the PU secrecy outage constraint to protect the PUs, we optimize the joint user and power allocation for the SUs to maximize the SU ergodic transmission rate. Simulation results are presented to verify the effectiveness of the proposed algorithm. It is shown that the proposed algorithm outperforms the existing scheme, especially for a large number of PUs and a small number of SUs. It is also shown that the number of eavesdroppers has negligible impact on the performance improvement of the proposed algorithm compared to the existing scheme. In addition, it is shown that increasing the number of eavesdroppers has insignificant impact on the SU performance if the number of eavesdroppers is already large.

Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs that are operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators have been studied. This paper presents an ultra-low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all-digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency-drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance.

Hybrid vehicles (HVs) and electric vehicles (EVs) have become widespread. These vehicles incorporate a large number of electronic devices, which requires the use of a high-voltage (200 V) battery. Power electronics devices driven by the 200 V battery is expected to increase in the future. As such, we herein propose a power line communication (PLC) method that uses a high-voltage power line. In the present paper, we first clarify the transmission channel through modeling of an equivalent circuit and channel measurement. We then conduct noise measurements and determine the noise characteristics of the proposed PLC. Finally, we evaluate the bit error rate performance through computer simulations based on the measured transmission channel and noise.

During the development of a human embryo, the position of eyes moves medially and caudally in the viscerocranium. A statistical model of this process can play an important role in embryology by facilitating qualitative analyses of change. This paper proposes an algorithm to construct a spatiotemporal statistical model for the eyeballs of a human embryo. The proposed modeling algorithm builds a statistical model of the spatial coordinates of the eyeballs independently for each Carnegie stage (CS) by using principal component analysis (PCA). In the process, a q-Gaussian distribution with a model selection scheme based on the Aaike information criterion is used to handle a non-Gaussian distribution with a small sample size. Subsequently, it seamlessly interpolates the statistical models of neighboring CSs, and we present 10 interpolation methods. We also propose an estimation algorithm for the CS using our spatiotemporal statistical model. A set of images of eyeballs in human embryos from the Kyoto Collection was used to train the model and assess its performance. The modeling results suggested that information geometry-based interpolation under the assumption of a q-Gaussian distribution is the best modeling method. The average error in CS estimation was 0.409. We proposed an algorithm to construct a spatiotemporal statistical model of the eyeballs of a human embryo and tested its performance using the Kyoto Collection.

In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um2 silicon area and consumes 0.18 mW at 1 GS/s.

An output voltage-current equation of charge pump DC-DC voltage multiplier using diodes is provided to cover wide clock frequency and output current ranges for designing energy harvester operating at a near-threshold voltage or in sub-threshold region. Equivalent circuits in slow and fast switching limits are extracted. The effective threshold voltage of the diode in slow switching limit is also derived as a function of electrical characteristics of the diodes, such as the saturation current and voltage slope parameter, and design parameters such as the number of stages, capacitance per stage, parasitic capacitance at the top plate of the main boosting capacitor, and the clock frequency. The model is verified compared with SPICE simulation.

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.

In this paper, the performance of orthogonal space-time block codes (OSTBC) for distributed multiple-input multiple-output (MIMO) systems employing adaptive M-QAM transmission is investigated over independent but not necessarily identically distributed (i.n.i.d.) generalized-K fading channels with arbitrary positive integer-valued k(inversely reflects the shadowing severity) and m (inversely reflects the fading severity). Before this, i.n.i.d. generalized-K fading channel has never been considered for distributed OSTBC-MIMO systems. Especially, the effects of the shape parameter k on the distributed OSTBC-MIMO system performance are unknown. Thus, we investigate mainly the significance of the shape parameter k on the distributed OSTBC-MIMO system performance, in terms of the average symbol error probability (SEP), outage probability, and spectral efficiency (SE). By establishing the system model, the approximated probability density function (PDF) of the equivalent signal to noise ratio (SNR) is derived and thereafter the approximated closed-form expressions of the above performance metrics are obtained successively. Finally, the derived expressions are validated via a set of Monte-Carlo simulations and the implications of the shape parameter k on the overall performance are highlighted.

A dual-hop amplify-and-forward (AF) relaying system with beamforming is analyzed over η-µ fading channels that includes Nakagami-m, Nakagami-q (Hoyt), and Rayleigh fading channels as special cases. New and exact expressions for the outage probability (OP) and average capacity are derived. Moreover, a new asymptotic analysis is also conducted for the OP and average capacity in terms of basic elementary functions which make it easy to understand the system behavior and the impact of channel parameters. The viability of the analysis is verified by Monte Carlo simulations.

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.

In this paper, a non-isolated bidirectional DC-DC converter with zero voltage switching and constant switching frequency is proposed. Unlike the active clamp bidirectional converters, to create soft switching condition in both direction, only one auxiliary switch is used, which reduces conduction losses and the complexity of the circuit. The proposed converter is controlled by pulse width modulation and the switches are gated complementary, thus the implementation of the control circuit is simple. Low switching losses, high efficiency, high power density, are the advantages of this converter. The simulation and experimental results of the converter verify theoretical analysis. Based on an implemented prototype of the proposed converter at 80 watts, the measured efficiency is 96.5%.

Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.

We integrate a pressure sensing capacitor and a low operation voltage OFET to develop a pressure sensor. The OFET was used as a readout device and an external pressure was loaded on the sensing capacitor. The OFET operates at less than 5 V and the change in the drain current in response to the pressure load (100 kPa) is two orders of magnitude.

In this paper, we investigate the problem of maximizing the weighted sum outage rate in multiuser multiple-input single-output (MISO) interference channels, where the transmitters have no knowledge of the exact values of channel coefficients, only the statistical information. Unfortunately, this problem is nonconvex and very difficult to deal with. We propose a new, provably convergent iterative algorithm where in each iteration, the original problem is approximated as second-order cone programming (SOCP) by introducing slack variables and using convex approximation. Simulation results show that the proposed SOCP algorithm converges in a few steps, and yields a better performance gain with a lower computational complexity than existing algorithms.

A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18µm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65µm × 75µm and consumes 1.1mW with the power supply of 1.8V. Temperature coefficient (TC) is 69.5ppm/°C from 0 to 100°C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192MHz within 12.67k-hits. At 192MHz, it shows a 1-MHz-offset phase noise of -102dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.