Without recourse to the Shannon-Nyquist sampling theorem, a novel information sampling (IS) concept is proposed for ultra-wideband (UWB) communications. To implement IS, a random pre-coding system architecture is designed and system performance is studied. Simulation results from one of UWB channel models show that the proposed system is effective to detect UWB signals with a low-sampling-rate analog-to-digital converter (ADC) at the receiver. Moreover, it can operate in a regime of heavy inter-symbol interference (ISI).

As the semiconductor technology continues to develop, hundreds of cores will be deployed on a single die in the future Chip-Multiprocessors (CMPs) design. Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide impressive high performance. An efficient and deadlock-free routing algorithm is a critical to achieve the high performance of network-on-chip. Traditional methods based on deterministic and turn model are deadlock-free, but they are unable to distribute the traffic loads over the network. In this paper, we propose an efficient, adaptive and deadlock-free algorithm (EAR) based on a novel routing selection strategy in 3D NoC, which can distribute the traffic loads not only in intra-layers but also in inter-layers according to congestion information and path diversity. Simulation results show that the proposed method achieves the significant performance improvement compared with others.

This paper presents a high-resolution and low-insertion-loss CMOS hybrid phase shifter with a nonuniform matching technique for satellite communication (SATCOM). The proposed hybrid phase shifter includes three 45° coarse phase-shifting stages and one 45° fine phase-tuning stage. The coarse stages are realized by bridged-T switch-type phase shifters (STPS) with 45° phase steps. The fine-tuning stage is based on a reflective-type phase shifter (RTPS) with two identical LC load tanks for phase tuning. A 0.8° phase resolution is realized by this work to support fine beam steering for the SATCOM. To further reduce the chain insertion loss, a nonuniform matching technique is utilized at the coarse stages. For the coarse and fine stages, the measured RMS gain errors at 29GHz are 0.7dB and 0.3dB, respectively. The measured RMS phase errors are 0.8° and 0.4°, respectively. The proposed hybrid phase shifter maintains return losses of all phase states less than -12dB from 24GHz to 34GHz. The presented hybrid phase shifter is fabricated in a standard 65-nm CMOS technology with a 0.14mm2 active area.

This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

This paper introduces a high-resolution and compact CMOS switch-type phase shifter (STPS) for the 5th generation mobile network (5G) n260 band. In this work, totally four coarse phase shifting stages and a high-resolution tuning stage are included. The coarse stages based on the bridged-T topology is capable of providing 202.5° phase coverage with a 22.5° tuning step. To further improve the phase shifting resolution, a compact fine-tuning stage covering 23° is also integrated with the coarse stages. Sub-degree phase shifting resolution is realized for supporting the fine beam-steering and high-accuracy phase calibration in the 5G new radio. Simplified phase control algorithm and suppressed insertion loss can also be maintained by the proposed fine-tuning stage. In the measurement, the achieved RMS gain errors at 39 GHz are 0.1 dB and 0.4 dB for the coarse stages and fine stage, respectively. The achieved RMS phase errors at 39 GHz are 3.1° for the coarse stages and 0.1° for the fine stage. Within 37 GHz to 40 GHz, the measured return loss within all phase-tuning states is always better than -14 dB. The proposed phase shifter consumes a core area of only 0.12mm2 with 65-nm CMOS process, which is area-efficient.

A color filter is the penetrable device adhering red, green, and blue organic color resists onto the surface of glass substrate for application of liquid crystal displays. It is fabricated by several technologies, including lithographic processes of coating, baking, exposing, etching, and rinsing. Inkjet printing technology has potentially implemented on the fabrication of the large-size panel with organic molecular film since this technology offers an efficient and steady production procedure. To achieve the basic specifications and requirements of high color performance, high color purity, high flatten, low reflective, and low production cost, inkjet printing technology will be seriously considered in the color filter manufacturing. Here we present the experimental results on physical and chromatic characteristics of color filters by implementing inkjet printing technology. To verify the chromatic characteristics of the resultant color filters, CIE 1931 chromaticity diagram is adopted to present the coordination of color distribution. For the green color ink, the results are x=0.30950.04, y=0.59120.04, brightness of Y=58.887 for 50 droplets and x=0.31030.04, y=0.57840.04, brightness of Y=60.328 for 41 droplets. For the blue color ink, the result is x=0.14900.04, y=0.10150.04, brightness of Y=8.808. For the red color ink, the result is x=0.5720.04, y=0.3200.04, brightness of Y=27.1.

Background subtraction algorithms generate a background model of the monitoring scene and compare the background model with the current video frame to detect foreground objects. In general, most of the background subtraction algorithms fail to detect foreground objects when the scene illumination changes. An entropy based background subtraction algorithm is proposed to address this problem. The proposed method adapts to illumination changes by updating the background model according to differences in entropy value between the current frame and the previous frame. This entropy based background modeling can efficiently handle both sudden and gradual illumination variations. The proposed algorithm is tested in six video sequences and compared with four algorithms to demonstrate its efficiency in terms of F-score, similarity and frame rate.

A novel five-point algorithm to remove phase noise in Chinese digital terrestrial media broadcasting system is proposed under the assumption that the bandwidth of phase noise is narrow. Simulation results demonstrate that the proposed method can provide 1-3 dB gains in AWGN and 1-4 dB in multi-path compared with those without compensation.

Recently, due to the development of design and manufacturing technologies for VLSI systems, an embedded system becomes more and more complex. Consequently, not only the performance of chips, but also the flexibility and dynamic adaptation of the implemented systems are required. To achieve these requirements, a partially reconfigurable device is promising. In this paper, we propose an efficient data structure to manage the reconfigurable units. And then, on the assumption that each task utilizes the rectangle shaped resources, a very simple MER enumeration algorithm based on this data structure is proposed. By utilizing the result of MER enumeration, the free space on the reconfigurable device can be used sufficiently. We analyze the complexity of the proposed algorithm and confirm its efficiency by experiments.

This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

This article presents a 28GHz high-accuracy phase and amplitude detection circuit for dual-polarized phased-array calibration. With dual-polarized calibration scheme, external LO signal is not required for calibration. The proposed detection circuit detects phase and amplitude independently, using PDC and ADC. By utilizing a 28GHz-to-140kHz downconversion scheme, the phase and amplitude are detected more accurately. In addition, reference signal for PDC and ADC is generated from 28GHz LO signal with divide-by-6 dual-step-mixing injection locked frequency divider (ILFD). This ILFD achieves 24.5-32.5GHz (28%) locking range with only 3.0mW power consumption and 0.01mm2 area. In the measurement, the detection circuit achieves phase and amplitude detections with RMS errors of 0.17degree and 0.12dB, respectively. The total power consumption of the proposed circuit is 59mW with 1-V supply voltage.

Multi-view video consists of multiple video sequences which are captured by multiple closely spaced cameras from different angles and positions. It enables each user to freely switch viewpoints by playing different video sequences. However, the transmission of multi-view video requires more bandwidth than conventional multimedia. To reduce the bandwidth, UDMVT (User Dependent Multi-view Video Transmission) based on MVC (Multi-view Video Coding) for a single user has been proposed. In UDMVT, the same frames are encoded into different versions for different users, which increases the redundant transmission. To overcome this problem and extend UDMVT to multiple users' environment, this paper proposes UMSM (User dependent Multi-view video Streaming for Multi-users). UMSM calculates the overlapping and un-overlapping frame area for multiple users from all frames based on feedback information at a server. Proposed UMSM exploits the combination of multicasting overlapping area to multiple users and unicasting un-overlapping area to each user. By means of this concept, UMSM only transmits required frames for each user. To achieve further reduction of the traffic, UMSM combines other two features with this concept. The first one is that offset of the requests from multiple users is aligned periodically to maximize the overlapping frame area. The second one is that the SP-frames standardized in H.264/AVC are exploited as the anchor frame of overlapping frame area to prevent redundant transmissions of overlapping frames. The combination of these three techniques achieves substantial reduction of the transmission bitrate for multiple users in multi-view video streaming. Simulation results using benchmark test sequences provided by MERL show that UMSM decreases the transmission bit-rate 47.2% on average for 4 users are watching the same multi-view video compared to UDMVT.

Fast switching speed, low power consumption, and good stability are some of the important properties of spin transfer torque assisted voltage controlled magnetic anisotropy magnetic tunnel junction (STT-assisted VCMA-MTJ) which makes the non-volatile full adder (NV-FA) based on it attractive for Internet of Things. However, the effects of process variations on the performances of STT-assisted VCMA-MTJ and NV-FA will be more and more obvious with the downscaling of STT-assisted VCMA-MTJ and the improvement of chip integration. In this paper, a more accurate electrical model of STT-assisted VCMA-MTJ is established on the basis of the magnetization dynamics and the process variations in film growth process and etching process. In particular, the write voltage is reduced to 0.7 V as the film thickness is reduced to 0.9 nm. The effects of free layer thickness variation (γtf) and oxide layer thickness variation (γtox) on the state switching as well as the effect of tunnel magnetoresistance ratio variation (β) on the sensing margin (SM) are studied in detail. Considering that the above process variations follow Gaussian distribution, Monte Carlo simulation is used to study the effects of the process variations on the writing and output operations of NV-FA. The result shows that the state of STT-assisted VCMA-MTJ can be switched under -0.3%≤γtf≤6% or -23%≤γtox≤0.2%. SM is reduced by 16.0% with β increases from 0 to 30%. The error rates of writing ‘0’ in the NV-FA can be reduced by increasing Vb1 or increasing positive Vb2. The error rates of writing ‘1’ can be reduced by increasing Vb1 or decreasing negative Vb2. The reduction of the output error rates can be realized effectively by increasing the driving voltage (Vdd).

To reduce mutual coupling of a two-level nested array (TLNA) with an even number of sensors, we propose an improved array configuration that exhibits all the good properties of the prototype optimal configuration under the constraint of a fixed number of sensors N and achieves reduction of mutual coupling. Compared with the prototype optimal TLNA (POTLNA), which inner level and outer level both have N/2 sensors, those of the improved optimal TLNA (IOTLNA) are N/2-1 and N/2+1. It is proved that the physical aperture and uniform degrees of freedom (uDOFs) of IOTLNA are the same as those of POTLNA, and the number of sensor pairs with small separations of IOTLNA is reduced. We also construct an improved optimal second-order super nested array (SNA) by using the IOTLNA as the parent nested array, termed IOTLNA-SNA, which has the same physical aperture and the same uDOFs, as well as the IOTLNA. Numerical simulations demonstrate the better performance of the improved array configurations.

Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.

Human detection has witnessed significant development in recent years. The introduction of cascade structure and integral histogram has greatly improved detection speed. But real-time detection is still only possible for sparse scan of 320 240 sized images. In this work, we propose a matrix-based structure to reorganize the computation structure of window-scanning detection algorithms, as well as a new pre-processing method called Hierarchical HOG Matrices (HHM) in place of integral histogram. Our speed-up scheme can process 320 240 sized images by dense scan (≈ 12000 windows per image) at the speed of about 30 fps, while maintaining accuracy comparable to the original HOG + cascade method.

An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.

In this paper, we propose a fast Maximal Empty Rectangle (MER) enumeration algorithm for online task placement on reconfigurable Field-Programmable Gate Arrays (FPGAs). On the assumption that each task utilizes rectangle-shaped resources, the proposed algorithm can manage the free space on FPGAs by an MER list. When assigning or removing a task, a series of MERs are selected and cut into segments according to the task and its assignment location. By processing these segments, the MER list can be updated quickly with low memory consumption. Under the proof of the upper limit of the number of the MERs on the FPGA, we analyze both the time and space complexity of the proposed algorithm. The efficiency of the proposed algorithm is verified by experiments.