This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

In this paper, the formulation of unified transport model is reviewed along with its implementation in a three-dimensional device simulator. The model features an accurate description of the energy exchange among electrons, holes and lattice, and is therefore suitable for self-consistently simulating thermal effects and non-stationary phenomena, as well as their possible interactions. Despite the model complexity, it is shown that the computational effort required for its solution is reasonably close to more conventional approaches. Application examples are also given, in which both unipolar and bipolar devices are simulated, discussing the relative importance of different phenomena and highlighting the simultaneous occurrence of carrier and lattice heating.

An efficient method which integrates a 2-D energy transport model, impact ionization model, gate current model, a discretized gate-capacitor EPROM model, and a post-processing quasi-transient programming/erase method, was developed for deep-submicron EPROM/Flash device simulation. The predicted results showed on the average better than 90% accuracy, and it took only few minutes CPU time on a SUN/SPARC2 to generate EPROM/Flash Vt shift curves.

This paper describes a DBF (Digital Beamforming) technique as a spatial filtering in the radar systems. DBF for a beamformer and an adaptive processor are discussed. An architecture for the beamformer is proposed. The beamformer discussed consists of systolic arrays that can form beams arbitrarily. Antenna radiation patterns measured in an open site are shown. For the adaptive processor, Gram-Schmidt transformation method is attained by using systolic arrays. Proposed is a means to prevent target signals from being suppressed in cells of the systolic arrays and to achieve the convergent characteristics independent of the magnitude of undesired signal power. In order to demonstrate the performance of the proposed processor, a test model of the adaptive processor was developed and tested in multiple undesired signal environment. Test results are indicated.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

A high-gain, low-noise amplifier for microelectrode probe, which integrated multimicroelectrode array for extracellular recording of neural activities and solid state circuits for the amplification of induced signals from the electrodes onto one substrate, was fabricated. In the amplifier, low-noise MOSFETs are used in the first stage, an interstage high-pass filter is incorporated to avoid saturation of the amplifier due to the polarization voltage of the electrode. In the second stage, an operational amplifier incorporating Bi-MOSFETs for the realization of high input impedance and large gain-bandwidth product is used. The gain of the fabricated amplifier is 56 dB for the frequency range between 2 Hz to 10 kHz, the noise voltage is 20µVpp; these satisfied design specifications.

Numerical simulation of the hydrodynamic semiconductor device equations requires powerful numerical schemes. A Space-time Galerkin/Least-Squares finite element formulation, that has been successfully applied to problems of fluid dynamic, is proposed for the solution of the hydrodynamic device equations. Similarity between the equations of fluid dynamic and semiconductor devices is discussed. The robustness and accuracy of the numerical scheme are demonstrated with the example of a single electron carrier submicron silicon MESFET device.

This paper introduces a constraint logic programming (CLP) language cu-Prolog as an implementation framework for constraint-based natural language processing. Compared to other CLP languages, cu-Prolog has several unique features. Most CLP languages take algebraic equations or inequations as constraints. cu-Prolog, on the other hand, takes Prolog atomic formulas in terms of user-defined predicates. cu-Prolog, thus, can describe symbolic and combinatorial constraints occurring in the constraint-based grammar formalisms. As a constraint solver, cu-Prolog uses the unfold/fold transformation, which is well known as a program transformation technique, dynamically with some heuristics. To treat the information partiality described with feature structures, cu-Prolog uses PST (Partially Specified Term) as its data structure. Sections 1 and 2 give an introduction to the constraint-based grammar formalisms on which this paper is based and the outline of cu-Prolog is explained in Sect. 3 with implementation issues described in Sect. 4. Section 5 illustrates its linguistic application to disjunctive feature structure (DFS) and parsing constraint-based grammar formalisms such as Japanese Phrase Structure Grammar (JPSG). In either application, a disambiguation process is realized by transforming constraints, which gives a picture of constraint-based NLP.

The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

The modular and growable photonic ATM switch architecture described in this paper uses both time-division and wavelength-division multiplexing technologies, so the switch capacity can be expanded in both the time and frequency domains. It uses a new implementation of output buffering scheme that overcomes the bottleneck in receiving and storing concurrent ultra fast optical cells. The capacity in one stage of a switch with this architecture can be increased from 32 gigabits per second to several terabits per second in a modular fashion. The proposed switch structure with output channel grouping can greatly reduce the amount of hardware and still guarantee the cell sequence.

This paper describes an implementation of the finite element method to examine the effects of actual lip shape on the sound radiation. A three-dimensional finite element approach by Galerkin method was used. The accuracy of the calculation of finite element method for the sound radiation was tested by comparing it with the exact solutions for a circular piston radiator on an infinite baffle. Using a set of finite element models of the vocal tract, we calculated the responses to a pure tone input and the sound fields over the frequency range of 100 Hz-7 kHz. The transfer functions are examined in detail for vowels /a/ and /i/ when the shape of the actual lips is simplified as a planeradiation surface. The effects of lip shape on the distribution of sound pressures are also shown in both the vocal tract and the surrounding space of the mouth opening.

From the viewpoint of customer's satisfaction, precise information and rapid action are very important when complaints about call connection failures or service quality deterioration come from customers. It is indispensable to the propose that operators are supported by an operation system which stores and processes each customer's information, their complaint's histories, network failure status and call connection detail data. This paper shows functions and Human Machine Interface (HMI) of Customer Complaint Handling System (CCHS). This system can handle a customer's complaint by an electric ticket and necessary information is automatically collected and shown on the ticket.

We consider a communication system in which a transmitter is connected to a receiver through parallel channels, and the Go-Back-N ARQ scheme is used to handle transmission errors. A packet error on one channel results in retransmission of packets assigned to other channels under the Go-Back-N ARQ scheme. Therefore, the channel-grouping (a grouped-channel is used to transmit the same packet at a time), would affect the throughput performance. We analyze the throughput performance, and give a tree-algorithm to efficiently search for the optimal channel-grouping which makes the throughput to become maximum. Numerical results show that the throughput is largely improved by using the optimal channel-grouping.

This paper presents a view on coming photonic network in which machines are potential customer to the network. The network will be providing unlimited number of virtual free spaces in which point to point and broadcasting modes of information interchanges are taking place simultaneously. It is also pointed out that the Asynchronous Transfer Mode (ATM) should be evolved to support this type of network by using true photonic switching technology.

Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.

Pure bend loss of a fiber with a trench section is calculated by the alternating-direction implicit finite-difference method. The dependence of the loss on the trench location is evaluated. The mechanism of the oscillatory behavior of the loss is discussed in terms of a modal approach in a dielectric slab waveguide.

A family of new generalized LR parsing algorithms are proposed which make use of a set of ancestors tables introduced by Kipps. As Kipps's algorithm does not give us a method to extract any parsing results, his algorithm is not considered as a practical parser but as a recognizer. In this paper, we will propose two methods to extract all parse trees from a set of ancestors tables in the top vertices of a graph-structured stack. For an input sentence of length n, while the time complexity of the Tomita parser can exceed O(n3) for some context-free grammars (CFGs), the time complexity of our parser is O(n3) for any CFGs, since our algorithm is based on the Kipps's recognizer. In order to extract a parse tree from a set of ancestors tables, it takes time in order n2. Some preliminary experimental results are given to show the efficiency of our parsers over Tomita parser.