A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.

Optical and electrical measurements of thin film n-channel SOI-MOSFETs reveal that the exponential tail in photon emission spectra originates from electron-hole recombination. Bremsstrahlung radiation model as a physical mechanism of photon emission was experimentally negated. Negative threshold voltage shift at the initial stage of high field stress is found to be caused by hole trapping in buried oxide. Subsequent turnover characteristics is explained by a competing process between electron trapping in the front gate oxide and hole trapping in the buried oxide. As to the degradation of transconductance, generated surface state as well as trapped holes in the buried oxide which reduce vertical electric field in SOI film are involved in the complicate degradation of transconductance.

We have studied a circuit partitioning approach in the view of parallel circuit simulation on a MIMD parallel computer. In parallel circuit simulation, a circuit is partitioned into equally sized subcircuits while minimizing the number of interconnection nodes. Besides circuit partitioning time should be short enough compared with the total simulation time. From the details of circuit simulation time, we found that balancing subcircuits is critical for low parallel processing, whereas minimizing the interconnection nodes is critical for highly parallel processing. Our circuit partitioning approach consists of four steps： Grouping transistors, initial partitioning the transistor-groups, minimizing the number of interconnection nodes, and balancing the subcircuits. It is based on an algorithmic approach, and can directly control the tradeoffs between balancing subcircuits and minimizing the interconnection nodes by adjusting the parameters. We partitioned a test circuit with 3277 transistors into 4, 9, ... , 64 subcircuits, and did parallel simulations using PARACS, our parallel circuit simulator, on an AP1000 parallel computer. The circuit partitioning time was short enough-less than 3 percent of the total simulation time. The highest performance of parallel analysis using 49 processors was 16 times that of a single processor, and that for total simulation was 9 times.

In order to construct a high-capacity and high-reliable indoor wireless communications system, it is essential to design the modulation/demodulation, coding and access schemes with high and variable data rate transmission capabilities, which meet the technical requirements inherent to wireless communications, i.e., high frequency utilization efficiency and robustness for fading. In this paper, we propose the frequency and time division multiple access with demand-assignment (FTDMA/DA) using multicarrier modulation as a frequency and time synchronous answer to meet the requirements, and analyze the performance of the FTDMA/DA system, taking account of teletraffic characteristics of multimedia information sources.

This paper deals with the size of switching functions in Exclusive-OR sum-of-products expressions (ESOPs). The size is the number of products in ESOP. There are no good algorithms to find an exact minimum ESOP. Since the exact minimization algorithms take a time in double exponential order, it is almost impossible to minimize ESOPs for an arbitrary n-variable functions with n5. Then,it is necessary to study the size of some concrete functions. These concrete functions are useful for testing heuristic minimization algorithms. In this paper we present the lower bounds on size of periodic functions in ESOPs. A symmetric function is said to be periodic when the vector of weights of inputs X such that f(X)1 is periodic. We show that the size of a 2t+1-periodic function with rank r is proportional to n2t+r, where t0 and 0r2t, i.e., in polynomial order,and thet the size of a (2s+1)2t-periodic function with s0 and t0 is greater than or equal to (3/2)n-(2s+1)2t, i.e., in exponential order. The concrete function the size of which is greater than or equal to 32(3/2)n-8 is presented. This function requires the largest size among the concrete functions the sizes of which are known. Some results for non-periodic symmetric functions are also given.

For the efficient circuit simulation, several direct/relaxation-based mixed mode simulation techniques have been studied. This paper proposes the combination of selective trace, which is well-known in the logic simulation, with dynamic network separation. In the selective trace method, the time points to be analyzed are selected for each subcircuit. Since the separation technique enables the analysis of each subcircuit independently, it is possible to skip solving the latent subcircuits, according to selective trace. Selecting the time points in accordance with activity of each subcircuit is analogous to multirate numerical integration technique used in the waveform relaxation algorithm.

As a generalization of the concept of pseudo-biorthogonal bases (PBOB), we already presented in Ref. [3] the theory of the so-called extended pseudo-biorthogonal bases (EPBOB). We introduce in this paper two special types of EPBOB called EPBOB's of type O and of type L. This paper discusses characterizations, construction methods, inherent properties, and mutual relations of these types of EPBOB.

A new evaluation technique of hot carrier degradation is proposed and applied to practical evaluation of p-channel polycrystalline silicon thin film transistors (TFT). The proposed technique introduces emission microscopy which is particularly effective for evaluating TFT devices. We have developed an automatic measurement system in which measurement of the electrical characteristics and monitoring the photo emission are done simultaneously. Using this system, we have identified the dominant mechanism of hot carrier degradation in TFTs, and evaluated the effect of plasma hydrogenation on hot carrier degradation.

The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg2SiO4 (Forsterite) and Zn2SiO4 (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

A design rule relaxation approach is one of the most important requirements for high density DRAMs. The approach relaxes the design rule of a element in comparison with the memory cell size and provides high density DRAMs with the minimum development of a scaled-down MOS structure and a fine patterning lithography process. This paper describes two design rule relaxation approaches, a close-packed folded (CPF) bit-line cell array layout and a Boosted Dual Word-Line scheme. The CPF cell array provides 1.26 times wider active area pitch and maximum 1.5 times wider isolation width. The Boosted Dual Word-Line scheme provides 2n times wider 1st Al pitch on memory cell array, double word-line driver pitch and 1.5 times larger design rule for 1st Al and contacts under 1st Al. Especially wide design rule of the Boosted Dual Word-Line scheme provides several times depth of focus (DOF) for 1st Al wiring which gives several times higher storage node and larger capacitance for capacitor over bit-line (COB) stacked capacitor cells. These approaches are successfully implemented in a 4 Mb DRAM test chip with a 0.91.8 µm2 memory cell.

Thin (Ba0.75Sr0.25)TiO3 (BST) films to be used as dielectric materials in 256 Mbit DRAM capacitors were investigated. These films were deposited by an rf-sputtering method at substrate temperatures of 480 to 750. As substrate temperature increases, the dielectric constant to the films also increases, from 230 to 550. BST films prepared at temperatures higher than 700 show larger current leaks than films prepared at lower temperatures. A dielectric constant of 250, corresponding to a silicon oxide equivalent thickness (teq) of 0.47 nm, and a leak current density about 110-8 A/cm2 were obtained in 30-nm-thick film deposited at 660. Both of these values are sufficient for use in a 256 Mbit DRAM capacitor.

Genetic algorithms have been shown to be very useful in a variety of search and optimization problems. In this paper, we describe the implementation of genetic algorithms for channel routing problems and identify the key points which are essential to making full use of the population of potential solutions, that is one of the characteristics of genetic algorithms. Three efficient crossover techniques which can be divided further into 13 kinds of crossover operators have been compared. We also extend our previous work with ability to deal with dogleg case by simply splitting multi-terminal nets into a series of 2-terminal subnets. It routes the Deutsch's difficult example with 21 tracks without any detours.

A sequence of nonnegative integers S=(s1, s2, , sn) is graphical if there is a graph with vertices v1,v2, ,vn such that deg(vi)=si for each i=1, 2, , n. The graphical degree sequence problem is： Given a sequence of nonnegative integers, determine whether it is graphical or not. In this paper, we consider several variations of the graphical degree sequence problem and give efficient algorithms.

This paper deals with methods for interconnection between two local private networks that are geographically separated. A scheme is first presented to chain low bit-rate physical circuits into one logical circuit, over which ATM cells are transmitted as if there is one circuit with a high bit-rate capacity. In particular, use of existing low bit-rate circuits, e.g., 384/1536 kbit/s PDH leased line services and N-ISDN switched channels, is considered. The paper discusses two methods to permit chaining of physical circuits, and identifies their advantages and applications. By using the ATM-based circuit-chaining method, dynamic capacity control of the interconnection is then introduced with the use of an ATM-based rate adaptation. This is intended to provide a flexible and cost-effective capacity control compared to the existing TDM-based control. It is also possible to realize non-stop operation of changing capacity by establishment and release of chained circuits, which will lead to high reliability and robustness of private networks. Finally, delay characteristics introduced by the method are evaluated based on a computer simulation which gives a short and acceptable delay.

This paper describes a future private network service and the system configurations for providing it. Technologies and service trends in local area and wide area networks are shown. As network services become more diversified and integrated, it becomes more difficult for users to use the networks effectively. This paper shows how this problem can be solved by using virtual network technology to attain seamless networking. It also presents the concept of group networking among many parties, which can be used as the basis for a virtual private network.

A method of range image segmentation using four Markov random field(MRF)s is described in this paper. MRFs are used in depth smoothing, gradient smoothing, edge detection and surface type labeling stage. First, range and its gradient images are smoothed preserving jump and roof edges respectively using line process concept one after another. Then jump and roof edges are extracted, combined and refined using penalizing undesirable edge patterns. Finally, curvatures are computed and the surface types are labeled according to the signs of principal curvatures. The surface type labels are refined using winner-takes-all layers in the stage. The final output is a set of regions with its exact surface type. The energy function is used in order to represent constraints of each stage and the minimum energy state is found using iterative method. Several experimental results show the generality of our approach and the execution speed of the proposed method is faster than that of a typical region merging method. This promises practical applications of our method.

A C1 interpolation scheme for constructing surface patch on n-sided region (n5, 6) is presented. The constructed surface patch matches the given boundary curves and cross-boundary slopes on the sides of the n-sided region (n5, 6). This scheme has relatively simple construction, and offers one degree of freedom for adjusting interior shape of the constructed interpolation surface. The polynomial precision set of the scheme includes all the polynomials of degree three or less. The experiments for comparing the proposed scheme with two schemes proposed by Gregory and Varady respectively and also shown.

Although the perception of gloss is based on human visual perception, some methods for extracting glossiness, in contrast to human ability, have been proposed involving curved surfaces. Glossiness defined in these methods, however, does not correspond with psychological glossiness perceived by the human eye over the wide range from relatively low gloss to high gloss. In addition, the obtained glossiness in these methods changes remarkably when the curvature radius of the high-gloss object becomes larger than 10mm. In reality, psychological glossiness does not change. These methods, furthermore, are available only for spherical objects. A new method for extracting glossiness is proposed in this study. For the new definition of glossiness, a spatial filter which simulates human retina function is utilized. The light intensity distribution of the curved object is convoluted with the spatial filter. The maximum value Hmax of the convoluted distribution has a high correlation with psychological glossiness Gph. From the relationship between Gph and Hmax, new glossiness Gf is defined. The gloss-extraction equipment consists of a light source, TV camera, an image processor and a personal computer. Cylinders with the curvature radii of 3-30 mm are used as the specimens in addition to spherical balls. In all specimens, a strong correlation, with a correlation coefficient of more than 0.97, has been observed between Gf and Gph over a wide range. New glossiness Gf conforms to Gph even if the curvature radius in more than 10 mm. Based on these findings, it is found that this method for extracting glossiness is useful for the extraction of glossiness of spherical and cylindrical objects over a wide range from relatively low gloss to high gloss.