This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

The stability conditions and stability factors of terminated active two port networks are investigated. They are expressed with the S parameters of active devices and the radii and centers of the circles defined by source and load terminations. The stability conditions are applied to specific cases. Some of the results correspond to the stability conditions expressed in Z, Y, H or G parameters and one of the other stability conditions of terminated two port network is similar to that for passive terminations which is expressed in S parameters. The various results derived in this paper are very useful for checking the stability of amplifiers, because both stability conditions and stability factors are simply calculated by using the S parameters without using the graphical method or transforming S parameters to Z, Y, H or G parameters. These stability conditions can be also used even if negative input or output resistance appears and even if the real part of source or load immittance is negative.

New critical-dimension controlling technique of off-axis illumination for aperiodic patterns has been developed. By means of arranging not-imaging additional pattern near 0.25 micron isolated patterns, the depth of focus of an isolated pattern was improved as well as the periodic patterns. Simulation and experimental results were verified on a 0.48 numerical-aperture, KrF excimer laser stepper. Using new deep-ultra-violet hardening technique for chemically amplified positive resist, the critical dimension loss of resist pattern was prevented. 0.25 micron design rule pattern was obtained with excellent mask linearity without critical-dimension-loss. The combination techniques are achieved quarter micron design rule complex circuit pattern layouts.

Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi2 on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi2 takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi2 lines. The discontinuity of TiSi2 abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi2 by annealing at 800 for 30 seconds, while it does not occur in TiSi2 gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.

This paper proposes a datagram delivery (class D service) architecture in an ATM-Internet, which is the network interconnecting ATM-LANs through the IWUs, Inter-Working Unit. We can provide a fast datagram delivery system through the following techniques. The datagram delivery to the destination terminal is performed by the datagram delivery server, so called CLS, which is located in the ATM-LAN where the destination terminal belongs to. Each CLS only manages the addresses for the terminals belonging to the corresponding ATM-LAN. The cells belonging to a certain datagram are transferred through a single (seamless) ATM connection from the source terminal to the CLS in the ATM-LAN where the destination terminal belongs to. The source terminal only resolves the access point address corresponding to the ATM-LAN where the destination terminal belongs to, when it submits the cells to the network to transfer the datagram to the corresponding destination terminal. The proposed datagram delivery architecture can be applied to the ATM-LAN system based on VPI routing architecture, easily. The number of the required ATM connections so as to provide datagram delivery through the proposed architecture is less than 1.0% of the ATM connections that the ATM-Internet can provide. Also, the required address space at UNI to provide datagram delivery are less than 1.0% of the UNI address space which is available to be used as an ATM connection identifier.

Water desorption from interlayer dielectric, spin-on-glass and SiO2 film deposited with tetraethylorthosilicate and O3, was controlled in order to reduce MOSFET hot-carrier degradation by using plasma SiO2 film as a water blocking layer. Two kinds of plasma SiO2 film were used in this study: SiH4 plasma SiO2 film deposited with SiH4 and N2O, and TEOS plasma SiO2 film deposited with TEOS and O2. Thermal desorption spectroscopy was used to study water desorption. Reduction of water desorption was obtained using plasma SiO2 film with water blocking ability; this reduction of water desorption resulted in suppression of the MOSFET hot-carrier degradation. The water blocking ability was obtained by low pressure deposition for SiH4 plasma SiO2 and low flow rate ratio of TEOS to O2 deposition for TEOS plasma SiO2. Water absorption studies of plasma SiO2 film using Fourier transform infrared spectroscopy revealed that water blocking ability is associated with small amount of water absorption both in SiH4 plasma SiO2 film and in TEOS plasma SiO2 film. Consequently, it is considered that the water blocking ability, as well as water absorption, of plasma SiO2 film depends on porosity.

This paper describes a new method to estimate traffic load of communication nodes, such as switching systems. The new method uses the system identification, which is often used in designing control systems of real systems. First, this paper makes clear that, under certain conditions, the input and output relation of a communication system, which is composed of a number of communication nodes, is formulated into a dynamic state equation that is classed as a time-invariant, single-input single-output, discrete-time system. Next, it is explained that traffic load information is estimated by identifying the dynamic state equations of the communication system. Then, the traffic load estimator is synthesized using the system identification in it. Finally, it is clarified by computation simulations that the proposed method is very applicable in estimating the traffic load of each communication node.

This paper discusses how to provide selective broadcast communication for a group of multiple entities in a distributed system by using high-speed communication networks. In the group communication, protocol data units (PDUs) sent by each entity have to be delivered atomically in some order to all the destinations in the group. In distributed applications, each entity sends a PDU only to a subset rather than all the entities, and each entity needs to receive all the PDUs destined to it from every entity in the same order as they are sent. We name such a broadcast service a selective order-preserving broadcast (SP) service. In this paper, we discuss how to design a distributed, asynchronous protocol which provides the SP service for entities.

IC performance simulation for statistical purpose is usually very time-consuming since the scale and complexity of IC have increased greatly in recent years. A common approach for reduction of simulation cost is aimed at the nature of simple modeling instead of actual circuit performance simulations. In this paper,a stochastic interpolation model (SIM) scheme is proposed which overcomes the drawbacks of the existing polynomial-based approximation schemes. First,the dependence of the R2press statistic upon a parameter in SIM is taken into account and by maximizing R2press this enables SIM to achieve the best approximation accuracy in the given sample points without any assumption on the sample data. Next, a sequential sampling strategy based on variance analysis is described to effectively construct SIM during its update process. In each update step, a new sample point with a maximal value of variance is added to the former set of the sample points. The update process will be continued until the desired approximation accuracy is reached. This would eventually lead to the realization of SIM with a quite small number of sample points. Finally, the coefficient of variance is introduced as another criterion for approximation accuracy check other than the R2press statistic. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.

A C1 interpolation scheme for constructing surface patch on n-sided region (n5, 6) is presented. The constructed surface patch matches the given boundary curves and cross-boundary slopes on the sides of the n-sided region (n5, 6). This scheme has relatively simple construction, and offers one degree of freedom for adjusting interior shape of the constructed interpolation surface. The polynomial precision set of the scheme includes all the polynomials of degree three or less. The experiments for comparing the proposed scheme with two schemes proposed by Gregory and Varady respectively and also shown.

This paper describes the current implementation and experimental results of a hardware/software codesign system for ASIP (Application Specific Integrated Processor) development： the PEAS-I System. The PEAS-I system accepts a set of application programs written in C language, associated data set, module database, and design constraints such as chip area and power consumption. The system then generates an optimized CPU core design in the form of an HDL as well as a set of application program development tools such as a C compiler, an assembler and a simulator. Another important feature of the PEAS-I system is that the system is able to give accurate estimations of chip area and performance before the detailed design of the ASIP is completed. According to the experimental results, the PEAS-I system has been found to be highly effective and efficient for ASIP development.

A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.

We studied the supply and removal of oil to and from a thin groove and the consequent insertion loss, aiming at matrix optical waveguide switches that utilize optical reflection and transmission effects at the groove. A robot precisely controlled the position of the removal nozzle and the supply needle by a vision servo. The optimum position for the removal nozzle was at the entrance of the groove to a circular oil pool, and the positioning margin was 10-15µm around the optimum position. The on-off ratio of the switching light power at the optimum position was about 30dB. The removal time was proportional to the kinetic viscosity of the oil, and the optimum height of the removal nozzle was independent of the kinetic viscosity of the oil. An analysis of the insertion loss revealed that the main factor in the loss at the reflection is the tilt of the groove wall.

In this paper, we present a new technique for the semantic analysis of sentences, including an ambiguity-packing method that generates a packed representation of individual syntactic and semantic structures. This representation is based on a dependency structure with constraints that must be satisfied in the syntax-semantics mapping phase. Complete syntax-semantics mapping is not performed until all ambiguities have been resolved, thus avoiding the combinatorial explosions that sometimes occur when unpacking locally packed ambiguities. A constraint satisfaction technique makes it possible to resolve ambiguities efficiently without unpacking. Disambiguation is the process of applying syntactic and semantic constraints to the possible candidate solutions (such as modifiees, cases, and wordsenses) and removing unsatisfactory condidates. Since several candidates often remain after applying constraints, another kind of knowledge to enable selection of the most plausible candidate solution is required. We call this new knowledge a preference. Both constraints and preferences must be applied to coordination for disambiguation. Either of them alone is insufficient for the purpose, and the interactions between them are important. We also present an algorithm for controlling the interaction between the constraints and the preferences in the disambiguation process. By allowing the preferences to control the application of the constraints, ambiguities can be efficiently resolved, thus avoiding combinatorial explosions.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

The photonic Space-Division (SD) switching network is attractive for constructing flexible broadband networks. This paper first describes possible applications of the network. A broadband STM switching system, Digital Cross-connect System (DCS) and Video signal distribution switch, especially for HDTV signals, are attractive near term applications. Recent activities on photonic SD switching network developments aiming at these application are also reviewed. A 128 line prototype switching system has been developed. This system utilizes LiNbO3 photonic switch matrices, semiconductor traveling wave amplifiers (TWAs) and three dimensional optical interconnections for multi stage switching networks. It is confirmed that the system has been operating in providing 150Mb/s TV phone services and 600Mb/s HDTV distribution services with high stability. An experimental optical Digital Crossconnect System (optical DCS) has also been demonstrated. Line failure restoration operation at 2.4Gb/s has been successfully demonstrated. These experimental demonstrations prove that practical photonic switching systems are feasible with current technologies.

A new mobility model dependent upon electron concentration is presented for studying the screening effect on ionized impurity scattering. By coupling this model with the drift-diffusion and Hartree models, the effects of self-consistent and quasi-equilibrium screening on carrier transport in heavily doped systems are revealed for first time. The transport mechanism is found to be dominated by the electron-concentration-dependent mobility, and transconductance is shown to be determined by effective mobility and changes from degraded to enhanced characteristics with electron concentration modulation.

An advanced model for self-heating effects in power semiconductor devices is derived from principles of irreversible thermodynamics. The importance of the entropy balance equation is emphasized. The governing equations for the coupled transport of charge carriers and heat are valid in both the stationary and transient regimes. Four characteristic effects contributing to the heat generation can be identified: Joule heating, recombination heating, Thomson heating and carrier source heating. Bandgap narrowing effects are included. Hot carrier effects are neglected. Numerical methods to solve the governing equations for the coupled transport of charge carriers and heat are described. Finally, results obtained in simulating latch-up in an IGT are discussed.