Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.

A photonic network with a space- and frequency switching capability is proposed. It provides point-to-point and point-to-multipoint connections without internal blocking. The switching network exclusively uses frequency switching stages and a shared-medium architecture. Our proposal is compared with similar published networks which are either also constructed solely from frequency switching stages or from frequency and space switching stages. It is shown that the proposed switching network features fewer optical and opto-electronic components, fewer different types of component/module, lower losses, a higher capacity and an easier expansibility.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

An advanced model for self-heating effects in power semiconductor devices is derived from principles of irreversible thermodynamics. The importance of the entropy balance equation is emphasized. The governing equations for the coupled transport of charge carriers and heat are valid in both the stationary and transient regimes. Four characteristic effects contributing to the heat generation can be identified: Joule heating, recombination heating, Thomson heating and carrier source heating. Bandgap narrowing effects are included. Hot carrier effects are neglected. Numerical methods to solve the governing equations for the coupled transport of charge carriers and heat are described. Finally, results obtained in simulating latch-up in an IGT are discussed.

Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.

From the viewpoint of customer's satisfaction, precise information and rapid action are very important when complaints about call connection failures or service quality deterioration come from customers. It is indispensable to the propose that operators are supported by an operation system which stores and processes each customer's information, their complaint's histories, network failure status and call connection detail data. This paper shows functions and Human Machine Interface (HMI) of Customer Complaint Handling System (CCHS). This system can handle a customer's complaint by an electric ticket and necessary information is automatically collected and shown on the ticket.

Directional dry etching of Tantalum is described X-ray lithography absorber patterns. Experiments are carried out using both reactive ion etching in CBrF3-based plasma and electron-cyclotron-resonance ion-stream etching in Cl2-based plasma. Ta absorber patterns with perpendicular sidewalls cannot be obtained by RIE when only CBrF3 gas is used as the etchant. While adding CH4 to CBrF3 effectively improves the undercutting of Ta patterns, it deteriorates etching stability because of the intensive deposition effect of CH4 fractions. By adding an Ar/CH4 mixture gas to CBrF3, it is possible to use RIE to fabricate 0.2-µm Ta absorber patterns with perpendicular sidewalls. ECR ion-stream etching is investigated to obtain high etching selectivity between Ta and SiO2 (etching mask)/SiN (membrane). Adding O2 to the Cl2 etchant improves undercutting without remarkably decreasing etching selectivity. Furthermore, an ECR ion-stream etching method is developed to stably etch Ta absorber patterns finer than 0.2µm. This is successfully applied to X-ray lithography mask fabrication for LSI test devices.

We consider a communication system in which a transmitter is connected to a receiver through parallel channels, and the Go-Back-N ARQ scheme is used to handle transmission errors. A packet error on one channel results in retransmission of packets assigned to other channels under the Go-Back-N ARQ scheme. Therefore, the channel-grouping (a grouped-channel is used to transmit the same packet at a time), would affect the throughput performance. We analyze the throughput performance, and give a tree-algorithm to efficiently search for the optimal channel-grouping which makes the throughput to become maximum. Numerical results show that the throughput is largely improved by using the optimal channel-grouping.

The power transfer characteristics of a symmetric nonlinear directional coupler (NLDC) are analyzed rigorously using the beam propagation method based on the finite difference scheme. The NLDC consists of two linear waveguides separated by a Kerr-like nonlinear gap layer. The change of nonlinear refractive index along the coupler is precisely evaluated by making use of the second-order iteration procedure with respect to a small propagation length. For the incidence of TE0 mode of the isolated linear waveguide, the highly accurate numerical results are obtained for the behavior of power transfer, and the coupling length and critical power for optical switching. The dependencies of the coupling length and critical power on the width of the gap layer and the input power levels are discussed, compared with those predicted by the coupled-mode approximations.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.

An efficient method which integrates a 2-D energy transport model, impact ionization model, gate current model, a discretized gate-capacitor EPROM model, and a post-processing quasi-transient programming/erase method, was developed for deep-submicron EPROM/Flash device simulation. The predicted results showed on the average better than 90% accuracy, and it took only few minutes CPU time on a SUN/SPARC2 to generate EPROM/Flash Vt shift curves.

In order to achieve an efficient and reliable prediction of device performance by numerical device simulation, a discretization mesh must be generated with an adequate, but not redundant, density of mesh points. However, manual mesh optimization requires user's trial and error. This task annoys the user considerably, especially when the device operation is not well known, or the required mesh-point density strongly depends on the bias condition, or else the manipulation of the mesh is difficult as is expected in 3D. Since these situations often happen in designing advanced VLSI devices, it is highly desirable to automatically optimize the mesh. Adaptive meshing techniques realize automatic optimization by refining the mesh according to the discretization error estimated from the solution. The performance of mesh optimization depends on a posteriori error indicators adopted to evaluate the discretization error. In particular, to obtain a precise terminal-current value, a reliable error indicator for the current continuity equation is necessary. In this paper, adaptive meshing based on the current continuity equation is investigated. A heuristic error indicator is proposed, and a methodology to extend a theoretical error indicator proposed for the finite element method to the requirements of device simulation is presented. The theoretical indicator is based on the energy norm of the flux-density error and is applicable to both Poisson and current continuity equations regardless of the mesh-element shape. These error indicators have been incorporated into the adaptive-mesh device-simulator HFIELDS, and their practicality is examined by MOSFET simulation. Both indicators can produce a mesh with sufficient node density in the channel region, and precise drain current values are obtained on the optimized meshes. The theoretical indicator is superior because it provides a better optimization performance, and is applicable to general mesh elements.

A unified model for frequency-dependent characteristics of transconductance and output resistance is presented that incorporates the dynamics of quasi-Fermi levels. Using this model, multiple-frequency dispersion and pulse-narrowing phenomena in GaAs MESFETs are demonstrated based on the drift-diffusion transport theory and a Schockley-Read-Hall-type deep trap model, where rate equations for multiple trapping processes are analyzed self-consistently. It is shown that the complex frequency dependence is due to both spatial and temporal effects of multiple traps.

Numerical simulation of the hydrodynamic semiconductor device equations requires powerful numerical schemes. A Space-time Galerkin/Least-Squares finite element formulation, that has been successfully applied to problems of fluid dynamic, is proposed for the solution of the hydrodynamic device equations. Similarity between the equations of fluid dynamic and semiconductor devices is discussed. The robustness and accuracy of the numerical scheme are demonstrated with the example of a single electron carrier submicron silicon MESFET device.

The theoretical modelling bandgap narrowing and percentage of ionized impurity atoms for uncompensated uniformly doped silicon containing conventional impurities (B, P, As, Sb) under thermodynamic-equilibrium conditions is presented. As distinct from existing approaches, this modelling is valid for impurity concentrations up to electrically-active-impurity-concentration limits and for the temperature range from 40 K up to 400 K. A relevant and efficient calculation software is proposed. The results of the calculations are compared with the results extracted by many authors from measurement data. A good agreement between these results is noted and possible reasons of some discrepancies are pointed out. The present modelling and software can be used for investigation of BJT charge-neutral regions as well as diffused or implanted resistors.

The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

For IF direct sampling phase detection method (IFSM) which realizes the arithmetical operations with digital filters by direct A/D (Analog to Digital) conversion of IF (Intermediate Frequency) signal, the method to eliminate DC offset is proposed and developed by using the gate array. A principle of the proposed method and the results of the measurement are shown.

It has been 15 years since we started producing the electric double-layer capacitors (also known as Super Capacitor) in 1978. Over the years we have introduced improvements that increased reliability and increased life. For example, after subjecting capacitors manufactured in 1984 and 1990 to load life tests (70, 5.5 V) for 2,000 hours, we discovered that the rate of change in capacitance (ΔC/C) of capacitors manufactured in 1990 was less than one-half that of capacitors manufactured in 1984. This shows that we have successfully increased the life of our electric double-layer capacitors. We conducted investigations regarding factors that contribute to volume of the electrolyte solution and better sealing properties. In the load life test, we observed that when the ratio of the weights of the electrolyte solution and the powdered activated carbon (hereinafter referred to as LB) was increased, the time it took before ΔC/C reached -30% was lengthened. This means that increasing LB also increases life. Furthermore, we also observed that when the gas permeability rate of the collector's rubber material was decreased in the load life test (70, 5.5 V), the time it took befor (ΔC/C) reached -30% was longer. Therefore life is dependent on the gas permeability rate (sealing property) of the collector rubber.

We found degraded output power due to discoloration of an abnormal epitaxial layer caused by supercooling of residual melt in liquid phase epitaxy (LPE) process of AlGaAs/GaAs heteroface solar cells developed to improve conversion efficiency of solar cells for satellites. We studied the discoloration mechanism and found effective methods for obtaning a good epitaxial layer. Using these results, we manufactured about 80,000 pieces of solar cells and employed them in the Japanese domestic Communication Satellite-3 (CS-3) launched by National Space Development Agency of Japan (NASDA). Five years after launch, these solar cells are still supplying the output power than predicted. This paper describes reliability improvements for the surface of epitaxial layer and successful results aftes 5 years of space operation.