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  • Efficient Two-Step Middle-Level Part Feature Extraction for Fine-Grained Visual Categorization

    Hideki NAKAYAMA  Tomoya TSUDA  

     
    PAPER-Image Recognition, Computer Vision

      Pubricized:
    2016/02/23
      Vol:
    E99-D No:6
      Page(s):
    1626-1634

    Fine-grained visual categorization (FGVC) has drawn increasing attention as an emerging research field in recent years. In contrast to generic-domain visual recognition, FGVC is characterized by high intra-class and subtle inter-class variations. To distinguish conceptually and visually similar categories, highly discriminative visual features must be extracted. Moreover, FGVC has highly specialized and task-specific nature. It is not always easy to obtain a sufficiently large-scale training dataset. Therefore, the key to success in practical FGVC systems is to efficiently exploit discriminative features from a limited number of training examples. In this paper, we propose an efficient two-step dimensionality compression method to derive compact middle-level part-based features. To do this, we compare both space-first and feature-first convolution schemes and investigate their effectiveness. Our approach is based on simple linear algebra and analytic solutions, and is highly scalable compared with the current one-vs-one or one-vs-all approach, making it possible to quickly train middle-level features from a number of pairwise part regions. We experimentally show the effectiveness of our method using the standard Caltech-Birds and Stanford-Cars datasets.

  • Non-Linear Extension of Generalized Hyperplane Approximation

    Hyun-Chul CHOI  

     
    LETTER-Image Recognition, Computer Vision

      Pubricized:
    2016/02/29
      Vol:
    E99-D No:6
      Page(s):
    1707-1710

    A non-linear extension of generalized hyperplane approximation (GHA) method is introduced in this letter. Although GHA achieved a high-confidence result in motion parameter estimation by utilizing the supervised learning scheme in histogram of oriented gradient (HOG) feature space, it still has unstable convergence range because it approximates the non-linear function of regression from the feature space to the motion parameter space as a linear plane. To extend GHA into a non-linear regression for larger convergence range, we derive theoretical equations and verify this extension's effectiveness and efficiency over GHA by experimental results.

  • A Novel Dictionary-Based Method for Test Data Compression Using Heuristic Algorithm

    Diancheng WU  Jiarui LI  Leiou WANG  Donghui WANG  Chengpeng HAO  

     
    BRIEF PAPER-Semiconductor Materials and Devices

      Vol:
    E99-C No:6
      Page(s):
    730-733

    This paper presents a novel data compression method for testing integrated circuits within the selective dictionary coding framework. Due to the inverse value of dictionary indices made use of for the compatibility analysis with the heuristic algorithm utilized to solve the maximum clique problem, the method can obtain a higher compression ratio than existing ones.

  • Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture

    Yo-Hao TU  Jen-Chieh LIU  Kuo-Hsing CHENG  

     
    BRIEF PAPER

      Vol:
    E99-C No:6
      Page(s):
    655-658

    This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.

  • Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method

    Sangheon OH  Changhwan SHIN  

     
    BRIEF PAPER

      Vol:
    E99-C No:5
      Page(s):
    541-543

    To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.

  • An Application of Laser Annealing Process in Low-Voltage Power MOSFETs

    Yi CHEN  Tatsuya OKADA  Takashi NOGUCHI  

     
    PAPER

      Vol:
    E99-C No:5
      Page(s):
    516-521

    An application of laser annealing process, which is used to form the P-type Base junction for high-performance low-voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), is proposed. An equivalent shallow-junction structure for P-Base junction with uniform impurity distribution is achieved by adopting green laser annealing of pulsed mode. Higher impurity activation for the shallow junction has been achieved by the laser annealing of melted phase than by conventional RTA (Rapid Thermal Annealing) of solid phase. The application of the laser annealing technology in the fabrication process of Low-Voltage U-MOSFET is also examined.

  • Efficient Evaluation of Maximizing Range Sum Queries in a Road Network

    Tien-Khoi PHAN  HaRim JUNG  Hee Yong YOUN  Ung-Mo KIM  

     
    PAPER-Data Engineering, Web Information Systems

      Pubricized:
    2016/02/16
      Vol:
    E99-D No:5
      Page(s):
    1326-1336

    Given a set of positive-weighted points and a query rectangle r (specified by a client) of given extents, the goal of a maximizing range sum (MaxRS) query is to find the optimal location of r such that the total weights of all points covered by r is maximized. In this paper, we address the problem of processing MaxRS queries over road network databases and propose two new external memory methods. Through a set of simulations, we evaluate the performance of the proposed methods.

  • Optimizing Hash Join with MapReduce on Multi-Core CPUs

    Tong YUAN  Zhijing LIU  Hui LIU  

     
    PAPER-Data Engineering, Web Information Systems

      Pubricized:
    2016/02/04
      Vol:
    E99-D No:5
      Page(s):
    1316-1325

    In this paper, we exploit MapReduce framework and other optimizations to improve the performance of hash join algorithms on multi-core CPUs, including No partition hash join and partition hash join. We first implement hash join algorithms with a shared-memory MapReduce model on multi-core CPUs, including partition phase, build phase, and probe phase. Then we design an improved cuckoo hash table for our hash join, which consists of a cuckoo hash table and a chained hash table. Based on our implementation, we also propose two optimizations, one for the usage of SIMD instructions, and the other for partition phase. Through experimental result and analysis, we finally find that the partition hash join often outperforms the No partition hash join, and our hash join algorithm is faster than previous work by an average of 30%.

  • A Distributed Capability Access Control Scheme in Information-Centric Networking

    Jung-Hwan CHA  Youn-Hee HAN  Sung-Gi MIN  

     
    PAPER-Network

      Vol:
    E99-B No:5
      Page(s):
    1121-1130

    Enforcing access control policies in Information-Centric Networking (ICN) is difficult due to there being multiple copies of contents in various network locations. Traditional Access Control List (ACL)-based schemes are ill-suited for ICN, because all potential content distribution servers should have an identical access control policy or they should contact a centralized ACL server whenever their contents are accessed by consumers. To address these problems, we propose a distributed capability access control scheme for ICN. The proposed scheme is composed of an internal capability and an external capability. The former is included in the content and the latter is added to a request message sent from the consumer. The content distribution servers can validate the access right of the consumer through the internal and external capabilities without contacting access control policies. The proposed model also enhances the privacy of consumers by keeping the content name and consumer identification anonymous. The performance analysis and implementation show that the proposed scheme is feasible and more efficient than other access control schemes.

  • An Application of Laser Annealing Process in Low-Voltage Planar Power MOSFETs

    Yi CHEN  Tatsuya OKADA  Takashi NOGUCHI  

     
    BRIEF PAPER-Semiconductor Materials and Devices

      Vol:
    E99-C No:5
      Page(s):
    601-603

    An application of laser annealing process, which is used to form the shallow P-type Base junction for 20-V planar power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is proposed. We demonstrated that the fabricated devices integrated with laser annealing process have superior electrical characteristics than those fabricated according to the standard process. Moreover, the threshold voltage variation of the devices applied by the new annealing process is effectively suppressed. This is due to that a uniform impurity distribution at the channel region is achieved by adopting laser annealing. Laser annealing technology can be applied as a reliable, effective, and advantageous process for the low-voltage power MOSFETs.

  • VdPAs: An Intermediate Data Source for Rendering Dynamic Vectors on Height Field

    Bin TANG  Jianxin LUO  Guiqiang NI  Weiwei DUAN  Yi GAO  

     
    LETTER-Computer Graphics

      Pubricized:
    2016/01/25
      Vol:
    E99-D No:5
      Page(s):
    1404-1407

    Vector data differs in the rasterized height field by data type. It is difficult to render dynamic vectors on height field because their shapes and locations may change at any time. This letter proposes a novel method: View-dependent Projective Atlases (VdPAs). As an intermediate data source, VdPAs act as rendering targets which enable height field and vectors to be rasterized at the same resolution. Then, VdPAs can be viewed as super-tiles. State of art height field rendering algorithms can be used for scenario rendering. Experimental results demonstrate that atlases are able to make dynamic vectors to be rendered on height field with real-time performance and high quality.

  • Properties of Generalized Feedback Shift Registers for Secure Scan Design

    Hideo FUJIWARA  Katsuya FUJIWARA  

     
    LETTER-Dependable Computing

      Pubricized:
    2016/01/21
      Vol:
    E99-D No:4
      Page(s):
    1255-1258

    In our previous work [12], [13], we introduced generalized feed-forward shift registers (GF2SR, for short) to apply them to secure and testable scan design. In this paper, we introduce another class of generalized shift registers called generalized feedback shift registers (GFSR, for short), and consider the properties of GFSR that are useful for secure scan design. We present how to control/observe GFSR to guarantee scan-in and scan-out operations that can be overlapped in the same way as the conventional scan testing. Testability and security of scan design using GFSR are considered. The cardinality of each class is clarified. We also present how to design strongly secure GFSR as well as GF2SR considered in [13].

  • A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

    Jungnam BAE  Saichandrateja RADHAPURAM  Ikkyun JO  Weimin WANG  Takao KIHARA  Toshimasa MATSUOKA  

     
    PAPER

      Vol:
    E99-C No:4
      Page(s):
    431-439

    A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.

  • Autonomous Decentralized Authorization and Authentication Management for Hierarchical Multi-Tenancy Open Access

    Qiong ZUO  Meiyi XIE  Wei-Tek TSAI  

     
    INVITED PAPER

      Vol:
    E99-B No:4
      Page(s):
    786-793

    Hierarchical multi-tenancy, which enables tenants to be divided into subtenants, is a flexible and scalable architecture for representing subsets of users and application resources in the real world. However, the resource isolation and sharing relations for tenants with hierarchies are more complicated than those between tenants in the flat Multi-Tenancy Architecture. In this paper, a hierarchical tenant-based access control model based on Administrative Role-Based Access Control in Software-as-a-Service is proposed. Autonomous Areas and AA-tree are used to describe the autonomy and hierarchy of tenants, including their isolation and sharing relationships. AA is also used as an autonomous unit to create and deploy the access permissions for tenants. Autonomous decentralized authorization and authentication schemes for hierarchical multi-tenancy are given out to help different level tenants to customize efficient authority and authorization in large-scale SaaS systems.

  • A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques

    Chia-Wen CHANG  Kai-Yu LO  Hossameldin A. IBRAHIM  Ming-Chiuan SU  Yuan-Hua CHU  Shyh-Jye JOU  

     
    PAPER-Integrated Electronics

      Vol:
    E99-C No:4
      Page(s):
    481-490

    This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm2). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (VDD =0.52 V), the ADPLL only dissipates 269.9 μW at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of -57.3 dBc with the period jitter of 0.217% UI.

  • MineSpider: Extracting Hidden URLs Behind Evasive Drive-by Download Attacks

    Yuta TAKATA  Mitsuaki AKIYAMA  Takeshi YAGI  Takeo HARIU  Shigeki GOTO  

     
    PAPER-Web security

      Pubricized:
    2016/01/13
      Vol:
    E99-D No:4
      Page(s):
    860-872

    Drive-by download attacks force users to automatically download and install malware by redirecting them to malicious URLs that exploit vulnerabilities of the user's web browser. In addition, several evasion techniques, such as code obfuscation and environment-dependent redirection, are used in combination with drive-by download attacks to prevent detection. In environment-dependent redirection, attackers profile the information on the user's environment, such as the name and version of the browser and browser plugins, and launch a drive-by download attack on only certain targets by changing the destination URL. When malicious content detection and collection techniques, such as honeyclients, are used that do not match the specific environment of the attack target, they cannot detect the attack because they are not redirected. Therefore, it is necessary to improve analysis coverage while countering these adversarial evasion techniques. We propose a method for exhaustively analyzing JavaScript code relevant to redirections and extracting the destination URLs in the code. Our method facilitates the detection of attacks by extracting a large number of URLs while controlling the analysis overhead by excluding code not relevant to redirections. We implemented our method in a browser emulator called MINESPIDER that automatically extracts potential URLs from websites. We validated it by using communication data with malicious websites captured during a three-year period. The experimental results demonstrated that MINESPIDER extracted 30,000 new URLs from malicious websites in a few seconds that conventional methods missed.

  • FPGA Implementation of Various Elliptic Curve Pairings over Odd Characteristic Field with Non Supersingular Curves

    Yasuyuki NOGAMI  Hiroto KAGOTANI  Kengo IOKIBE  Hiroyuki MIYATAKE  Takashi NARITA  

     
    PAPER-Cryptography and cryptographic protocols

      Pubricized:
    2016/01/13
      Vol:
    E99-D No:4
      Page(s):
    805-815

    Pairing-based cryptography has realized a lot of innovative cryptographic applications such as attribute-based cryptography and semi homomorphic encryption. Pairing is a bilinear map constructed on a torsion group structure that is defined on a special class of elliptic curves, namely pairing-friendly curve. Pairing-friendly curves are roughly classified into supersingular and non supersingular curves. In these years, non supersingular pairing-friendly curves have been focused on from a security reason. Although non supersingular pairing-friendly curves have an ability to bridge various security levels with various parameter settings, most of software and hardware implementations tightly restrict them to achieve calculation efficiencies and avoid implementation difficulties. This paper shows an FPGA implementation that supports various parameter settings of pairings on non supersingular pairing-friendly curves for which Montgomery reduction, cyclic vector multiplication algorithm, projective coordinates, and Tate pairing have been combinatorially applied. Then, some experimental results with resource usages are shown.

  • Impact and High-Pitch Noise Suppression Based on Spectral Entropy

    Arata KAWAMURA  Noboru HAYASAKA  Naoto SASAOKA  

     
    PAPER-Engineering Acoustics

      Vol:
    E99-A No:4
      Page(s):
    777-787

    We propose an impact and high-pitch noise-suppression method based on spectral entropy. Spectral entropy takes a large value for flat spectral amplitude and a small value for spectra with several lines. We model the impact noise as a flat spectral signal and its damped oscillation as a high-pitch periodic signal consisting of spectra with several lines. We discriminate between the current noise situations by using spectral entropy and adaptively change the noise-suppression parameters used in a zero phase-based impact-noise-suppression method. Simulation results show that the proposed method can improve the perceptual evaluation of the speech quality and speech-recognition rate compared to conventional methods.

  • Object Tracking with Embedded Deformable Parts in Dynamic Conditional Random Fields

    Suofei ZHANG  Zhixin SUN  Xu CHENG  Lin ZHOU  

     
    LETTER-Image Recognition, Computer Vision

      Pubricized:
    2016/01/19
      Vol:
    E99-D No:4
      Page(s):
    1268-1271

    This work presents an object tracking framework which is based on integration of Deformable Part based Models (DPMs) and Dynamic Conditional Random Fields (DCRF). In this framework, we propose a DCRF based novel way to track an object and its details on multiple resolutions simultaneously. Meanwhile, we tackle drastic variations in target appearance such as pose, view, scale and illumination changes with DPMs. To embed DPMs into DCRF, we design specific temporal potential functions between vertices by explicitly formulating deformation and partial occlusion respectively. Furthermore, temporal transition functions between mixture models bring higher robustness to perspective and pose changes. To evaluate the efficacy of our proposed method, quantitative tests on six challenging video sequences are conducted and the results are analyzed. Experimental results indicate that the method effectively addresses serious problems in object tracking and performs favorably against state-of-the-art trackers.

  • Topic Representation of Researchers' Interests in a Large-Scale Academic Database and Its Application to Author Disambiguation

    Marie KATSURAI  Ikki OHMUKAI  Hideaki TAKEDA  

     
    PAPER

      Pubricized:
    2016/01/14
      Vol:
    E99-D No:4
      Page(s):
    1010-1018

    It is crucial to promote interdisciplinary research and recommend collaborators from different research fields via academic database analysis. This paper addresses a problem to characterize researchers' interests with a set of diverse research topics found in a large-scale academic database. Specifically, we first use latent Dirichlet allocation to extract topics as distributions over words from a training dataset. Then, we convert the textual features of a researcher's publications to topic vectors, and calculate the centroid of these vectors to summarize the researcher's interest as a single vector. In experiments conducted on CiNii Articles, which is the largest academic database in Japan, we show that the extracted topics reflect the diversity of the research fields in the database. The experiment results also indicate the applicability of the proposed topic representation to the author disambiguation problem.

541-560hit(2849hit)