In this paper, we present a new frequency identification technique using the recent methodology of compressive sensing and discrete prolate spheroidal sequences with optimal energy concentration. Using the bandpass form of discrete prolate spheroidal sequences as basis matrix in compressive sensing, compressive frequency sensing algorithm is presented. Simulation results are given to present the effectiveness of the proposed technique for application to detection of carrier-frequency type signal and recognition of wideband signal in communication.

The sensing scheme based on the generalized likelihood ratio test (GLRT) technique has attracted a lot of research interest in the field of cognitive radios (CR). Although its potential advantages in detecting correlated primary signal have been illustrated in prior work, no theoretical analysis of the positive effects of the correlation has appeared in the literature. In this letter, we derive the theoretical false-alarm and detection probabilities of GLRT detector. The theoretical analysis shows that, in the low signal-to-noise ratio (SNR) region, the detector's performance can be improved by exploiting the high correlations between the primary signal samples. The conclusions of the analysis are verified by numerical simulation results.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.

We propose a compact matrix-switch-based hierarchical optical cross-connect (HOXC) architecture that effectively handles the colorless waveband add/drop ratio restriction so as to realize switch scale reduction. In order to implement the colorless waveband add/drop function, we develop a wavelength MUX/DMUX that can be commonly used by different wavebands. We prove that the switch scale of the proposed HOXC is much smaller than that of conventional single-layer optical cross-connects (OXCs) and a typical HOXC. Furthermore, we introduce a prototype system based on the proposed architecture that utilizes integrated novel wavelength MUXs/DMUXs. Transmission experiments prove its technical feasibility.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [1] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.

A method of estimating dual primitives in a textural image is proposed. This method is based on the Primitive, Grain, and Point Configuration (PGPC) texture model, which regards a texture as an arrangement of grains derived from one or a few primitives. Appropriate primitives can be represented by morphological structuring elements estimated from a texture. Conventional primitive estimation methods estimate only one primitive from each textural image. However, they do not work well on textural images that contain more than one basic structure, since two or more types of grain cannot be generated from only one primitive. The proposed method simultaneously estimates two optimal structuring elements of a texture. The experimental results show that the proposed method provides more representative estimations than the conventional method.

As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.

This paper introduces a practical color filter array (CFA) interpolation technique. Among the many technologies proposed in this field, the inter-color methods that exploit correlation between color planes generally outperform the intra-color approaches. We have found that the filtering direction, e.g., horizontal or vertical, is among the most decisive factors for the performance of the CFA interpolation. However, most of the state-of-the-art technologies are not flexible enough in determining the filtering direction. For example, filtering only in the upper direction is not usually supported. In this context, we propose an inter-color CFA interpolation using a local map called unified geometry map (UGM). In this method, the filtering direction is determined based on the similarity of the local map data. Thus, it provides more choices of the filtering directions, which enhances the probability of finding the most appropriate direction. It is confirmed through simulations that the proposal outperforms the state-of-the-art algorithms in terms of objective quality measures. In addition, the proposed scheme is as inexpensive as the conventional methods with regard to resource consumption.

Tracking a non-rigid object in a video in the presence of background clutter and partial occlusion is challenging. We propose a non-rigid object-tracking paradigm by repeatedly detecting and associating saliency regions. Saliency region segmentation is operated in each frame. The segmentation results provide rich spatial support for tracking and make the reliable tracking of non-rigid object without drifting possible. The precise object region is obtained simultaneously by associating the saliency region using two independent observers. Our formulation is quite general and other salient-region segmentation algorithms also can be used. Experimental results have shown that such a paradigm can effectively handle tracking problems of objects with rapid movement, rotation and partial occlusion.

The influence of quantization scaling is seldom considered in narrow band (NB) communications, because a high resolution analogue-to-digital converter (ADC) can be generally employed. In ultra-wideband (UWB) systems, however, the resolution of ADC is required to be low to reduce complexity, cost and power consumption. Consequently, the influence of quantization scaling is significant and should be taken into account. In this letter, effects of quantization scaling are analyzed in terms of signal to noise ratio (SNR) loss based on an uniformly distributed random signal model. For the effects of quantization scaling on bit error rate (BER) performance, however, theoretical analysis is too complicated since quantization is a nonlinear operation, hence we employ here a simulation method. The simulation results show there exists an optimum scaling to minimize BER performance for a fixed-resolution receiver; the optimum scaling power is related to the SNR of input noisy signal and the resolution of ADC.

An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 1818 logic blocks and an area of 54.76 mm2.

We describe a parameter estimation method for a target object in an area that sensors monitor. The parameters to be estimated are the perimeter length, size, and parameter determined by the interior angles of the target object. The estimation method does not use sensor location information, only the binary information on whether each sensor detects the target object. First, the sensing area of each sensor is assumed to be line-segment-shaped, which is a model of an infrared distance measurement sensor. Second, based on the analytical results of assuming line-segment-shaped sensing areas, we developed a unified equation that works with general sensing areas and general target-object shapes to estimate the parameters of the target objects. Numerical examples using computer simulation show that our method yields accurate results.

This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18 µm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100 k-gate blocks, which is 7.1 X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

On uniformly convex real Banach spaces, a fixed point theorem in weak topology for successively recurrent system of fuzzy-set-valued nonlinear mapping equations and its application to ring nonlinear network systems are theoretically discussed in detail. An arbitrarily-level likelihood signal estimation is then established.

A novel circularly polarized antenna with square slot for broadband characteristics is proposed in this paper. The horizontal and vertical components of the L-shaped probe, which is a key element to generate circular polarization, are separated in the structure, contrary to the concept of joined probes. Another novelty, placing stubs in the slot, which are attached to the ground plane, is proposed to improve the axial ratio (AR) characteristics of the antenna by around 10%. Placing a reflector at a distance of λ0/4 from the antenna to obtain unidirectional patterns is effective when no stubs are placed in the slot. The antenna attains a < 10 dB return loss bandwidth of 47.5% (2.76-4.48 GHz) and < 3 dB axial ratio (AR) bandwidth of 42.47% (2.67-4.11 GHz) in measurement. Parametric studies on key parameters and measured results are also presented.

A resource allocation scheme for multi-access MIMO-OFDM systems in uplink was developed to improve power and spectrum efficiency in the frequency and the space domains [1]. The scheme requires a multi-user detector in the receiver and assumes identical spatial crosscorrelation across all subcarriers for any pair of spatially separable users. However, the multi-user detection device may not exist in the receiver and the identical spatial crosscorrelation assumption may not be valid in some operational scenarios. The paper develops a scheme to remedy these problems for multi-access MIMO-OFDM systems without using multi-user detection techniques and the assumption. The proposed scheme aims at minimizing the total user transmit power while satisfying the required data rate, the maximum transmit power constraint, and the bit error rate of each user. The simulation results are presented to demonstrate the efficacy of the proposed algorithm.

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

Various low power technologies have been developed and applied to LSIs from the point of device and circuit design. A lot more CPU cores as well as function IPs are integrated on a single chip LSI today. Therefore, not only the device and circuit low power technologies, but software power control technologies are becoming more important to reduce active power of application systems. This paper overviews the low power technologies and defines power management platform as a combination of hardware functions and software programming interface. This paper discusses importance of the power management platform and direction of its development.

Today, practical semiconductor products are an integral part of our lives and the infrastructure of society, and this trend will continue in the future. New areas of application will expand into medical, environmental, and agriculture (food)-related fields in addition to the conventional information and communication technology (ICT)-related field. Low-cost semiconductor devices with advanced functions have thus far been realized by miniaturization. However, we are now approaching the physical limit of miniaturization, and also, the investment required for new semiconductor manufacturing facilities has become huge. Under such circumstances, we propose an approach based on semiconductor devices called microcube chips and ideas of semiconductor development, i.e., agile integration and "inch-fab." Our approach is expected to contribute to expanding the range of companies that can fabricate semiconductor devices to include small-size companies, exploring new applications of semiconductor devices, and providing a wide variety of semiconductor devices at a low cost from the semiconductor industry.