Simple half-duplex repetition-based relaying protocols can achieve spatial diversity at the expense of additional relaying signals in the time domain. In this paper, a linear unitary precoder based on a singular vector for cooperative systems with the amplify-and-forward (AF) relaying protocol is proposed in order to improve spectral efficiency. An exact expression of the precoder design is first derived for the case of equal power allocation. Then, water-filling power allocation is used in conjunction with the precoder to further increase the system capacity, where the precoder matrix is generated with an iterative process. From the implementation point of view, the channel state information (CSI) has to be estimated and quantized in systems, the detail of which is described in the sequel. The adaptive modulation and coding (AMC) technique with the proposed precoder is also discussed to achieve high throughput performance. Finally, numerical and simulation results are presented to demonstrate the effectiveness of the proposed technique in improving capacity and throughput.

In the face of constant malicious attacks to network-connected software systems, software vulnerabilities need to be discovered early in the development phase. In this paper, we present AspFuzz, a state-aware protocol fuzzer based on the specifications of application-layer protocols. AspFuzz automatically generates anomalous messages that exploit possible vulnerabilities. The key observation behind AspFuzz is that most attack messages violate the strict specifications of application-layer protocols. For example, they do not conform to the rigid format or syntax required of each message. In addition, some attack messages ignore the protocol states and have incorrect orders of messages. AspFuzz automatically generates a large number of anomalous messages that deliberately violate the specifications of application-layer protocols. To demonstrate the effectiveness of AspFuzz, we conducted experiments with POP3 and HTTP servers. With AspFuzz, we can discover 20 reported and 1 previously unknown vulnerabilities for POP3 servers and 25 reported vulnerabilities for HTTP servers. Two vulnerabilities among these can be discovered by the state-awareness of AspFuzz. It can also find a SIP state-related vulnerability.

Utilizing available channels to improve the network performance is one of the most important targets for the cognitive MAC protocol design. Using antenna technologies is an efficient way to reach this target. Therefore, in this paper, we propose a novel cognitive MAC protocol, called Polarization-based Long-range Communication Directional MAC Protocol (PLRC-DMAC), for Cognitive Ad Hoc Networks (CAHNs). The proposed protocol uses directional antennas to acquire better spatial reuse and establish long-range communication links, which can support more nodes to access the same channel simultaneously. Moreover, the PLRC-DMAC also uses polarization diversity to allow nodes in the CAHN to share the same channel with Primary Users (PUs). Furthermore, we also propose a Long-range Orientation (LRO) algorithm to orient the long-range nodes. Simulation results show that the LRO algorithm can accurately orient the long-range nodes, and the PLRC-DMAC can significantly increase the network throughput as well as reduce the end-to-end delay.

Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F2 and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45 nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.

This paper presents a Multiple-Input Multiple-Output (MIMO) propagation model for independent and identically distributed (i.i.d.) channels in the mixture of none-Line-of-Sight (NLOS) and Line-of-Sight (LOS) environments. The derived model enables to evaluate the system statistical characteristics of Signal-to-Noise-Ratio (SNR) for MIMO transmission based on Maximal Ratio Combing (MRC). An application example applying the model in 22 configuration to ITS Inter-Vehicle Communication (IVC) system is introduced. We clarify the effectiveness of the proposed model by comparisons of both computer simulations and measurement results of a field experiment. We also use the model to show the better performance of SNR when applying MIMO to IVC system than SISO and SIMO.

Based on the reiterative maximum signal minus interference level (MSMIL) criterion and adaptive beamforming, a novel interference suppression algorithm is proposed for shared-spectrum multistatic radar that must contend with clutter. In this algorithm, two-dimensional adaptive beamformers are designed for azimuths and range cells. Numerical results show advantages of the proposed method.

We report a fast single element nonvolatile memory that employs amorphous to crystalline phase change. Temperature change is induced within a single electronic element in confined geometry transistors to cause the phase change. This novel phase change memory (PCM) operates without the need for charge transport through insulator films for charge storage in a floating gate. GeSbTe (GST) was employed to the phase change material undergoing transition below 200. The phase change, causing conductivity and permittivity change of the film, results in the threshold voltage shift observed in transistors and capacitors.

We propose the collective electron tunneling model in the electron injection process between the Nano Dots (NDs) and the two-dimensional electron gas (2DEG). We report the collective motion of electrons between the 2DEG and the NDs based on the measurement of the Si-ND floating gate structure in the previous studies. However, the origin of this collective motion has not been revealed yet. We evaluate the proposed tunneling model by the model calculation. We reveal that our proposed model reproduces the collective motion of electrons. The insight obtained by our model shows new viewpoints for designing future nano-electronic devices.

We have studied the transport property of the Vertical MOSFET (V-MOSFET) with an impurity from the viewpoint of quantum electron dynamics. In order to obtain the position dependence of impurity for the electron transmission property through the channel of the V-MOSFET, we solve the time-dependent Shrodinger equation in real space mesh technique We reveal that the impurity in the source edge can assist the electron transmission from the source to drain working as a wave splitter. In addition, we also reveal the effect of an impurity in the surface of pillar is limited because of its dimensionality. Furthermore, we obtained that the electron injection from the source to the channel becomes difficult due to the energy difference between the subbands of the source and the channel. These results enable us to obtain the guiding principle to design the V-MOSFET in the 10 nm pillar. The results enable us to obtain the guiding principle to design the V-MOSFET beyond 20 nm design rule.

In summary, we successfully developed the polymer nonvolatile 4F2 memory-cell. It was based on nonvolatile memory characteristics such as memory margin and retention time, which was observed in memory-cell embedded with Ag nanocrystals in PVK layer. The nonvolatile memory characteristics depend on the shape, distribution and isolation of Ag nanocrystals. Accordingly, the thickness of Ag film has an important role in optimizing the Ag nanocrystals. Therefore, the polymer nonvolatile memory-cell is fabricated by appropriate thickness of film and need an improvement of interface between Ag nanocrystals and PVK for sufficient nonvolatile memory characteristics.

We have demonstrated high mobility MOS transistors on high quality epitaxial SiGe films selectively grown on Si (100) substrates. The hole mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by an optimized Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. Surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS further enhance transistor performances. On a (110) surface, the hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain. We finally address low drive current issue of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (ρc).

High resolution direction-of-arrival (DOA) estimation algorithm for array antennas becomes popular in these days. However, there are several error factors such as mutual coupling among the elements in actual array. Hence array calibration is indispensable to realize intrinsic performance of the algorithm. In the many applications, it is preferable that the calibration can be done in the practical environment in operation. In such a case, the incident wave becomes coherent multipath wave. Calibration of array in the multipath environment is a hard problem, even when DOA of elementary waves is known. To realize array calibration in the multipath environment will be useful for some applications even if reference signals are required. In this report, we consider property of reference waves in the multipath environment and derive a new calibration technique by using the multipath coherent reference waves. The reference wave depends on not only the DOA but also complex amplitude of each elementary wave. However, the proposed technique depends on the DOA only. This is the main advantage of the technique. Simulation results confirm the effectiveness of the proposed technique.

Various low power technologies have been developed and applied to LSIs from the point of device and circuit design. A lot more CPU cores as well as function IPs are integrated on a single chip LSI today. Therefore, not only the device and circuit low power technologies, but software power control technologies are becoming more important to reduce active power of application systems. This paper overviews the low power technologies and defines power management platform as a combination of hardware functions and software programming interface. This paper discusses importance of the power management platform and direction of its development.

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

This paper presents an improved Gini-Index algorithm to correct feature-selection bias in text classification. Gini-Index has been used as a split measure for choosing the most appropriate splitting attribute in decision tree. Recently, an improved Gini-Index algorithm for feature selection, designed for text categorization and based on Gini-Index theory, was introduced, and it has proved to be better than the other methods. However, we found that the Gini-Index still shows a feature selection bias in text classification, specifically for unbalanced datasets having a huge number of features. The feature selection bias of the Gini-Index in feature selection is shown in three ways: 1) the Gini values of low-frequency features are low (on purity measure) overall, irrespective of the distribution of features among classes, 2) for high-frequency features, the Gini values are always relatively high and 3) for specific features belonging to large classes, the Gini values are relatively lower than those belonging to small classes. Therefore, to correct that bias and improve feature selection in text classification using Gini-Index, we propose an improved Gini-Index (I-GI) algorithm with three reformulated Gini-Index expressions. In the present study, we used global dimensionality reduction (DR) and local DR to measure the goodness of features in feature selections. In experimental results for the I-GI algorithm, we obtained unbiased feature values and eliminated many irrelevant general features while retaining many specific features. Furthermore, we could improve the overall classification performances when we used the local DR method. The total averages of the classification performance were increased by 19.4 %, 15.9 %, 3.3 %, 2.8 % and 2.9 % (kNN) in Micro-F1, 14 %, 9.8 %, 9.2 %, 3.5 % and 4.3 % (SVM) in Micro-F1, 20 %, 16.9 %, 2.8 %, 3.6 % and 3.1 % (kNN) in Macro-F1, 16.3 %, 14 %, 7.1 %, 4.4 %, 6.3 % (SVM) in Macro-F1, compared with tf*idf, χ2, Information Gain, Odds Ratio and the existing Gini-Index methods according to each classifier.

In this paper, we present a cache based motion compensation (MC) architecture for Quad-HD H.264/AVC video decoder. With the significantly increased throughput requirement, VLSI design for MC is greatly challenged by the huge area cost and power consumption. Moreover, the long memory system latency leads to performance drop of the MC pipeline. To solve these problems, three optimization schemes are proposed in this work. Firstly, a high-performance interpolator based on Horizontal-Vertical Expansion and Luma-Chroma Parallelism (HVE-LCP) is proposed to efficiently increase the processing throughput to at least over 4 times as the previous designs. Secondly, an efficient cache memory organization scheme (4S×4) is adopted to improve the on-chip memory utilization, which contributes to memory area saving of 25% and memory power saving of 3949%. Finally, by employing a Split Task Queue (STQ) architecture, the cache system is capable of tolerating much longer latency of the memory system. Consequently, the cache idle time is saved by 90%, which contributes to reducing the overall processing time by 2440%. When implemented with SMIC 90 nm process, this design costs a logic gate count and on-chip memory of 108.8 k and 3.1 kB respectively. The proposed MC architecture can support real-time processing of 3840×2160@60 fps with less than 166 MHz.

There are a great amount of various resources described in many different ways for service oriented grid environment, while traditional grid resource discovery methods could not fit more complex future grid system. Therefore, this paper proposes a novel grid resource discovery method based on association rule hypergraph partitioning algorithm which analyzes user behavior in history transaction records to provide personality service for user. And this resource discovery method gives a new way to improve resource retrieval and management in grid research.

In this paper, we present a new frequency identification technique using the recent methodology of compressive sensing and discrete prolate spheroidal sequences with optimal energy concentration. Using the bandpass form of discrete prolate spheroidal sequences as basis matrix in compressive sensing, compressive frequency sensing algorithm is presented. Simulation results are given to present the effectiveness of the proposed technique for application to detection of carrier-frequency type signal and recognition of wideband signal in communication.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [1] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.