As the channel frequency selectivity becomes severer, the bit error rate (BER) performance of direct sequence spread spectrum (DSSS) signal transmission with rake combining degrades due to an increasing inter-path interference (IPI). Frequency-domain equalization (FDE) can replace rake combining with much improved BER performance in a severe frequency-selective fading channel. For FDE, accurate estimation of the channel transfer function is required. In this paper, we propose an iterative channel estimation that uses pilot chips which are time-multiplexed within each chip block for fast Fourier transform (FFT). The pilot acts as a cyclic-prefix of FFT block as well. The achievable BER performance is evaluated by computer simulation. It is shown that the proposed channel estimation has a very good tracking ability against fast fading.

In this paper, a weighted element-wise block adaptive frequency-domain equalization (WEB-FDE) is proposed for a single-carrier system with the cyclic-prefix. In the WEB-FDE, the one-tap equalizer corresponding to a frequency-bin first preserves input DFT elements (element-wise block). Its coefficient in each block is then calculated by minimizing a weighted squared norm of the a posteriori error. Simulation results in a time-varying typical urban (TU) channel show that the bit-error-rate (BER) performance of the WEB-FDE outperform that of the normalized least-mean-square (NLMS)-FDE and recursive-least-square (RLS)-FDE.

In this paper, we propose a stochastic dynamic local search (SDLS) method for Multiple-Valued Logic (MVL) learning by introducing stochastic dynamics into the traditional local search method. The proposed learning network maintains some trends of quick descent to either global minimum or a local minimum, and at the same time has some chance of escaping from local minima by permitting temporary error increases during learning. Thus the network may eventually reach the global minimum state or its best approximation with very high probability. Simulation results show that the proposed algorithm has the superior abilities to find the global minimum for the MVL network learning within reasonable number of iterations.

In numerical simulations of microwave structures using the alternating-direction implicit finite-difference time-domain (ADI-FDTD) method, the time marching scheme comprises two sub-iterations, where different updating schemes for evaluating E and H fields at each sub-iteration can be adopted. In this paper, the E-field implicit-updating (EFIU) and H-field implicit-updating (HFIU) schemes are compared with each other especially with regard to the implementation of local boundary conditions.

A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg

We propose and experimentally demonstrate a simple method for monitoring optical signal-to-noise ratio. The novel method can be used in the optical transport networks using optical cross-connects or reconfigurable optical add-drop multiplexers. OSNR is measured by monitoring the transmitted optical power and the reflected optical power from fiber Bragg grating. We have obtained OSNR with an error less than 0.8 dB.

A precoding scheme is described for multiple-input and multiple-output orthogonal frequency-division multiplexing systems with a QR-decomposition maximum likelihood detector (MLD) incorporated with a parallel interference canceller (PIC) at a receiver. Transmit antenna ranking based on received substream signal power or per-substream minimum Euclidean distances is fed back to a transmitter. Based on the ranking information, precoding matrices are determined as permutation matrices such that specific packets are transmitted from transmit antennas with higher channel quality over the whole subcarriers. The simulation results demonstrated that precoding effectively utilizes PIC by reducing the possibility that all substreams are incorrectly decoded and thus improves the transmission performance of a QR-decomposition MLD with PIC.

A two-stage least square identification method is proposed for estimating ARMA (autoregressive moving average) coefficients from speech signals. A pulse-train like input sequence is often employed to account for the source effects in estimating vocal tract parameters of voiced speech. Due to glottal and radiation effects, the pulse train, however, does not represent the effective voice source. The authors have already proposed a simple but effective model of voice source for estimating AR (autoregressive) coefficients. This letter extends our approach to ARMA analysis to wider varieties of speech sounds including nasal vowels and consonants. Analysis results on both synthetic and natural nasal speech are presented to demonstrate the analysis ability of the method.

In this paper, we show that speed and yield of reconfigurable devices can be enhanced by utilizing within-die (WID) delay variations. An LUT Array LSI is fabricated to confirm whether FPGAs have clear WID variations to be utilized. We can measure delay variations by counting the number of LUTs a signal propagates within a certain time. Clear die-to-die (D2D) and WID variations are observed. We propose a variation model from the measurement results. Adequacy of the model is discussed from randomness of the random component. Effect of the speed and yield enhancement is confirmed using the proposed model. Yield increases from 80.0% to 100.0% by optimizing configurations.

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

To drastically reduce the power dissipation (P) of an absolute difference accumulation (ADA) circuit for H.26x/MPEG4 motion estimation, a fast block-matching (BM) algorithm called the Multiple Block-matching Step (MBS) algorithm has been developed. The MBS algorithm can drastically improve the block matching speed, while achieving the same visual quality as that of a full search (FS) BM algorithm. Power dissipation (P) of a 0.18-µm CMOS absolute difference accumulator (ADA) circuit employing the MBS algorithm is significantly reduced to the range of about 0.3% to 12% that of the same ADA circuit adopting FS.

We propose a new tableau construction which builds an FSM, instead of a Kripke structure, from a formula in a class of temporal logic named ASTL. This FSM is a maximal model of the formula under the preorder derived from simulation relations. Additionally, we propose a method using the tableaus to build controllers in a certain topology of interconnected FSMs. We can use ASTL to describe the desired behaviors of the control system. This method is applicable to generating digital circuits. Moreover, this method accepts a wider range of specifications than conventional methods.

Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced by register relocation maintaining the circuit behavior and topology. In this paper, we propose a gate-level register relocation method to reduce the minimum feasible clock period. The proposed method is a greedy local circuit modification method. We prove that the proposed method achieves the clock period achieved by retiming with delay decomposition, if the delay of each element in the circuit is unique. Experiments show that the computation time of the proposed method and the number of registers of a circuit obtained by the proposed method are smaller than those obtained by the retiming method in the conventional synchronous framework.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10-1 and over 3.3-0.8 dB at BER=10-3.

This paper presents two steganographic methods for JPEG2000 still images which approximately preserve histograms of discrete wavelet transform coefficients. Compared with a conventional JPEG2000 steganography, the two methods show better histogram preservation. The proposed methods are promising candidates for secure JPEG2000 steganography against histogram-based attack.

We have developed a new simulation methodology for predicting shot noise intensity in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). In our approach, shot noise in MOSFETs is calculated by employing a two dimensional device simulator in conjunction with the shot noise model of a p-n junction. The accuracy of the noise model has been demonstrated by comparing simulation results with measured noise data of p-n diodes. The intensity of shot noise in various n-MOSFET devices under various bias conditions was estimated beyond GHz operational frequency by using our simulation scheme. At DC or low-frequency region, sub-threshold current dominates the intensity of shot noise. Therefore, shot noise is independent on frequency in this region, and its intensity is exponentially depends on VG, proportional to L-1, and almost independent on VD. At high-frequency region above GHz frequency, on the other hand, shot noise intensity depends on frequency and is much larger than that of low-frequency region. In particular, the intensity of the RF shot noise is almost independent on L, VD and VG. This suggests that high-frequency shot noise intensity of MOSFETs is decided only by the conditions of source-bulk junction.

Due to its importance in engineering applications, the bilinear transformation has been studied in many literature. In this letter two new algorithms are presented to compute transformation matrix for the bilinear s-z transformation.

Fractional Motion Estimation (FME) is an advanced feature adopted in H.264/AVC video compression standard with quarter-pixel accuracy. Although FME could gain considerably higher encoding efficiency, sub-pixel interpolation and sum of absolute transformed difference (SATD) computation, as main parts of FME, increase the computation complexity a lot. To reduce the complexity of FME, this paper proposes a full computation reusable VLSI oriented algorithm. Through exploiting the similarity among motion vectors (MVs) of partitions in the same macroblock (MB), temporary computation results can be fully reused. Furthermore, a simple and effective searching method is adopted to make the proposed method more suitable for VLSI implementation. Experiment results show that up to 80% add operations and 85% internal reference frame memory access operations are saved without any degradation in the coding quality.

This paper presents a simple and effective method to further reduce the search points in multilevel successive elimination algorithm (MSEA). Because the calculated sea values of those best matching search points are much smaller than the current minimum SAD, we can simply increase the calculated sea values to increase the elimination ratio without much affecting the coding quality. Compared with the original MSEA algorithm, the proposed strict MSEA algorithm (SMSEA) can provide average 6.52 times speedup. Compared with other lossy fast ME algorithms such as TSS and DS, the proposed SMSEA can maintain more stable image quality. In practice, the proposed technique can also be used in the fine granularity SEA (FGSEA) algorithm and the calculation process is almost the same.