The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

In this paper, we study an opportunistic scheduling scheme for the TDMA wireless network with relay stations. We model the time-varying channel condition of a wireless link as a stochastic process. Based on this model, we formulate an optimization problem for the opportunistic scheduling scheme that maximizes the expected system throughput while satisfying the QoS constraint of each user. In the opportunistic scheduling scheme for the system without relay stations, each user has only one communication path between the base station and itself, and thus only user selection is considered. However, in our opportunistic scheduling scheme for the system with relay stations, since there may exist multiple paths between the base station and a user, not only user selection but also path selection for the scheduled user is considered. In addition, we also propose an opportunistic time-sharing method for time-slot sharing between base station and relay stations. With the opportunistic time-sharing method, our opportunistic scheduling provides opportunistic resource sharing in three places in the system: user selection in a time-slot, path selection for the selected user, and time-slot sharing between base station and relay stations. Simulation results show that as the number of places that opportunistic resource sharing is applied to increases, the performance improvement also increases.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

IEEE 802.15.4a standard enables location-aided routing or topology control in ZigBee networks, since it uses time-of-arrival (TOA)-based ranging technique. However, TOA based techniques may yield location error due to the non-line-of-sight (NLOS) effects, and hence degrade the network performance. In this letter, we demonstrate the impact of NLOS on the localization performance and propose a location error detection and compensation algorithm for IEEE 802.15.4a networks. The proposed algorithm detects NLOS by using the min-max algorithm and compensates the location error by using the Kalman filter. Experimental results show that the proposed algorithm significantly reduces the localization errors in indoor environments.

This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p=1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs.

In this letter, we propose a novel approach to estimate three different kinds of phone mismatch penalty matrices for two-stage keyword spotting. When the output of a phone recognizer is given, detection of a specific keyword is carried out through text matching with the phone sequences provided by the specified keyword using the proposed phone mismatch penalty matrices. The penalty matrices associated with substitution, insertion and deletion errors are estimated from the training data through deliberate error generation. The proposed approach has shown a significant improvement in a Korean continuous speech recognition task.

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.

Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

A multiple-valued current-mode (MVCM) circuit using current-flow control is proposed for a power-greedy sequential linear-array system. Whenever operation is completed in processing element (PE) at the present stage, every possible current source in the PE at the previous stage is cut off, which greatly reduces the wasted power dissipation due to steady current flows during standby states. The completion of the operation can be easily detected using "operation monitor" that observes input and output signals at latches, and that generates control signal immediately at the time completed. Since the wires of data and control signals are shared in the proposed MVCM circuit, no additional wires are required for current-flow control. In fact, it is demonstrated that the power consumption of the MVCM circuit using the proposed method is reduced to 53 percent in comparison with that without current-source control.

This paper presents the new switching converter model used for analyzing the generation mechanism of ringing ground leakage (GL) current, generated during the transient, at switch on/off of any switching converter. By applying the Norton model, the proposed new model of switching converter can be formulated. The ringing GL current is evaluated at the switching on/off of the unbalanced (half-bridge converter) and the balanced converter (full-bridge converter) for bidirectional D.C. motor drive used as an example. It is concluded that the measured and simulated results of the generated GL current agree well with the numerical analysis results, analyzed by the proposed new model of switching converter, in terms of the minimum or maximum peak currents and the ringing frequency.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 µm and L = 0.18 µm in a 1616 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 to 75. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput.

Novel thermopiles based on modulation doped AlGaAs/InGaAs, AlGaN/GaN, and ZnMgO/ZnO heterostructures are proposed and designed for the first time, for uncooled infrared image sensor application. These devices are expected to offer high performances due to both the superior Seebeck coefficient and the excellently high mobility of 2DEG and 2DHG due to high purity channel layers at the heterojunction interface. The AlGaAs/InGaAs thermopile has the figure-of-merit Z of as large as 1.110-2/K (ZT = 3.3 over unity at T = 300 K), and can be realized with a high responsivity R of 15,200 V/W and a high detectivity D* of 1.8109 cmHz1/2/W with uncooled low-cost potentiality. The AlGaN/GaN and the ZnMgO/ZnO thermopiles have the advantages of high sheet carrier concentration due to their large polarization charge effects (spontaneous and piezo polarization charges) as well as of a high Seebeck coefficient due to their strong phonon-drag effect. The high speed response time τ of 0.9 ms with AlGaN/GaN, and also the lower cost with ZnMgO/ZnO thermopiles can be realized. The modulation-doped heterostructure thermopiles presented here are expected to be used for uncooled infrared image sensor applications, and for monolithic integrations with other photon detectors such as InGaAs, GaN, and ZnO PiN photodiodes, as well as HEMT functional integrated circuit devices.

This letter deals with mobile location estimation based on a minimax mean-squared error (MSE) algorithm using time-of-arrival (TOA) measurements for mitigating the nonline-of-sight (NLOS) effects in cellular systems. Simulation results are provided for illustrating the minimax MSE estimator yields good performance than the other least squares and weighted least squares estimators under relatively low signal-to-noise ratio and moderately NLOS conditions.

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.

This letter presents a theoretical analysis of the Parallel Iterative Matching (PIM)'s dynamics with multiple iterations used in an input-buffered packet switch. In our approach, by carefully categorizing all unmatched patterns into several representative patterns after each iteration, probabilities of accumulated matched pairs in a recursive manner are successfully obtained. Numerical evaluations of the analytical formulas are performed.

Several methods for testing stability of first quadrant quarter-plane two dimensional (2-D) recursive digital filters have been suggested in 1970's and 80's. Though Jury's row and column algorithms, row and column concatenation stability tests have been considered as highly efficient mapping methods. They still fall short of accuracy as they need infinite number of steps to conclude about the exact stability of the filters and also the computational time required is enormous. In this paper, we present procedurally very simple algebraic method requiring only two steps when applied to the second order 2-D quarter - plane filter. We extend the same method to the second order Non-Symmetric Half-plane (NSHP) filters. Enough examples are given for both these types of filters as well as some lower order general recursive 2-D digital filters. We applied our method to barely stable or barely unstable filter examples available in the literature and got the same decisions thus showing that our method is accurate enough.

This work addresses the enormous efficiency and linearity potential of optimized AlGaN/GaN high-electron mobility transistors (HEMT) in conventional Doherty linear base-station amplifiers at 2.7 GHz. Supported by physical device simulation, the work further elaborates on the use of AlGaN/GaN HEMTs in high-speed current-switch-mode class-D (CMCD)/class-S MMICs for data rates of up to 8 Gbit/s equivalent to 2 GHz RF-operation. The device needs for switch-mode operation are derived and verified by MMIC results in class-S and class-D operation. To the authors' knowledge, this is the first time 2 GHz-equivalent digital-switch-mode RF-operation is demonstrated with GaN HEMTs with high efficiency.

An assume-guarantee verification method has been recognized as a promising approach to verify component-based software by model checking. This method is not only fitted to component-based software but also has a potential to solve the state space explosion problem in model checking. The method allows us to decompose a verification target into components so that we can model check each of them separately. In this method, assumptions are seen as the environments needed for the components to satisfy a property and for the rest of the system to be satisfied. The number of states of the assumptions should be minimized because the computational cost of model checking is influenced by that number. Thus, we propose a method for generating minimal assumptions for the assume-guarantee verification of component-based software. The key idea of this method is finding the minimal assumptions in the search spaces of the candidate assumptions. The minimal assumptions generated by the proposed method can be used to recheck the whole system at much lower computational cost. We have implemented a tool for generating the minimal assumptions. Experimental results are also presented and discussed.