In this paper, we studied the use of common-mode noise reduction technique for in-vehicle electronic equipment in an actual instrument design. We have improved the circuit model of the common-mode noise that flows to the wire harness to add the effect of a bypass capacitor located near the LSI. We analyzed the improved circuit model using a circuit simulator and verified the effectiveness of the noise reduction condition derived from the circuit model. It was also confirmed that offsetting the impedance mismatch in the PCB section requires to make a circuit constant larger than that necessary for doing the impedance mismatch in the LSI section. An evaluation circuit board comprising an automotive microcomputer was prototyped to experiment on the common-mode noise reduction effect of the board. The experimental results showed the noise reduction effect of the board. The experimental results also revealed that the degree of impedance mismatch in the LSI section can be estimated by using a PCB having a known impedance. We further inquired into the optimization of impedance parameters, which is difficult for actual products at present. To satisfy the noise reduction condition composed of numerous parameters, we proposed a design method using an optimization algorithm and an electromagnetic field simulator, and confirmed its effectiveness.

The dynamic channel allocation (DCA) scheme in multi-cell systems causes serious inter-cell interference (ICI) problem to some existing calls when channels for new calls are allocated. Such a problem can be addressed by advanced centralized DCA design that is able to minimize ICI. Thus, in this paper, a centralized DCA is developed for the downlink of multi-cell orthogonal frequency division multiple access (OFDMA) systems with full spectral reuse. However, in practice, as the search space of channel assignment for centralized DCA scheme in multi-cell systems grows exponentially with the increase of the number of required calls, channels, and cells, it becomes an NP-hard problem and is currently too complicated to find an optimum channel allocation. In this paper, we propose an ant colony optimization (ACO) based DCA scheme using a low-complexity ACO algorithm which is a kind of heuristic algorithm in order to solve the aforementioned problem. Simulation results demonstrate significant performance improvements compared to the existing schemes in terms of the grade of service (GoS) performance and the forced termination probability of existing calls without degrading the system performance of the average throughput.

A new estimation algorithm of clock drift in symbol duration for high precision ranging, based on multiple symbols of chirp spread spectrum (CSS) is proposed. Since the permissible error of a crystal oscillator in CSS is relatively high given the need to lower device costs, ranging results are perturbed by clock drift. We establish the phenomenon of clock drift in multiple symbols of CSS, and estimate the clock drift in symbol duration based on phase difference between adjacent symbols. The proposed algorithm is analyzed, and verified by Monte Carlo simulations.

Provider authentication is necessary in bidirectional broadcasting services, and a digital signature scheme is often used to prevent an adversary from attempting impersonation. The cost of secure signing key management is extremely high. In addition, the key has to be updated very often, since it is frequently used. The result is that the verification key also has to be updated very often, and its redistribution cost is huge. These costs are real and substantive problems, especially when the number of users is large. In this paper, we propose a system that dramatically reduces these costs. In the system, the signing key is updated, but the corresponding verification key does not have to be updated. This means that the signing key can be updated without any cost for redistributing the verification key and that the system is secure against the threat of signing key leakage, since the key can be frequently updated. Moreover, we propose a new key management method that divides a conventional key management server's role into two. The use of a key-insulated signature (KIS) scheme enables low-cost and more secure key management with two servers. Finally, to make a bidirectional broadcasting service more secure even if the signing key is leaked, we developed a new strong KIS scheme. We performed an experiment that assessed the cost of our strong KIS scheme and found that it is sufficiently low. Accordingly, a provider authentication system employing this scheme would be more efficient and would have lower key redistribution and network costs in comparison with conventional authentication systems.

In this paper, we develop asymptotic analysis and simulation models to better understand the characteristics of performance and energy consumption in a multi-core processor design in which dynamic voltage scaling is used. Our asymptotic model is derived using Amdahl's law, Rent's rule and power equations to derive the optimum number of cores and their voltage levels. Our model can predict the possible impact of different multi-core processor configurations on the performance and energy consumption for given workload characteristics (e.g. available parallelism) and process technology parameters (e.g. ratios of dynamic and static energies to total energy). Through the asymptotic analysis and optimization based on the models, we can observe an asymptotic relationship between design parameters such as "the number of cores," "core size" and "voltage scaling strategies" of a multi-core architecture with regards to performance and energy consumption at an initial phase of the design.

Consider a client who intends to perform a massive computing task comprsing a number of sub-tasks, while both storage and computation are outsourced by a third-party service provider. How could the client ensure the integrity and completeness of the computation result? Meanwhile, how could the assurance mechanism incur no disincentive, e.g., excessive communication cost, for any service provider or client to participate in such a scheme? We detail this problem and present a general model of execution assurance for massive computing tasks. A series of key features distinguish our work from existing ones: a) we consider the context wherein both storage and computation are provided by untrusted third parties, and client has no data possession; b) we propose a simple yet effective assurance model based on a novel integration of the machineries of data authentication and computational private information retrieval (cPIR); c) we conduct an analytical study on the inherent trade-offs among the verification accuracy, and the computation, storage, and communication costs.

We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm110 µm. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area.

Chinese new words and their part-of-speech (POS) are particularly problematic in Chinese natural language processing. With the fast development of internet and information technology, it is impossible to get a complete system dictionary for Chinese natural language processing, as new words out of the basic system dictionary are always being created. A latent semi-CRF model, which combines the strengths of LDCRF (Latent-Dynamic Conditional Random Field) and semi-CRF, is proposed to detect the new words together with their POS synchronously regardless of the types of the new words from the Chinese text without being pre-segmented. Unlike the original semi-CRF, the LDCRF is applied to generate the candidate entities for training and testing the latent semi-CRF, which accelerates the training speed and decreases the computation cost. The complexity of the latent semi-CRF could be further adjusted by tuning the number of hidden variables in LDCRF and the number of the candidate entities from the Nbest outputs of the LDCRF. A new-words-generating framework is proposed for model training and testing, under which the definitions and distributions of the new words conform to the ones existing in real text. Specific features called "Global Fragment Information" for new word detection and POS tagging are adopted in the model training and testing. The experimental results show that the proposed method is capable of detecting even low frequency new words together with their POS tags. The proposed model is found to be performing competitively with the state-of-the-art models presented.

An operational amplifier is one of the key functional blocks and is widely used in analog and mixed-signal circuits. For low-power consumption, many techniques such as class AB and slew-rate enhancement have been proposed. Although phase compensation is related to power consumption, it has not been clearly discussed from the viewpoint of the power consumption. In this paper, the conventional and the improved Miller compensations and the phase compensation by introducing a new zero are dicussed for low-power operational amplifiers.

This paper describes non-reference objective quality evaluation for noise-reduced speech. First, a subjective test is conducted in accordance with ITU-T Rec. P.835 to obtain the speech quality, the noise quality, and the overall quality of noise-reduced speech. Based on the results, we then propose an overall quality estimation model. The unique point of the proposed model is that the estimation of the overall quality is done only using the previously estimated speech quality and noise quality, in contrast to conventional models, which utilize the acoustical features extracted. Finally, we propose a non-reference objective quality evaluation method using the proposed model. The results of an experiment with different noise reduction algorithms and noise types confirmed that the proposed method gives more accurate estimates of the overall quality compared with the method described in ITU-T Rec. P.563.

With the big success of 802.11 wireless networks, there have been many proposals addressing end-to-end QoS guarantees in 802.11 WLAN. However, we have found that current end-to-end QoS architectures lack of one or more important properties such as cross-layer interaction, end-to-end integration, reconfigurability and modularity. In this work, we present an end-to-end reference QoS architecture for 802.11 WLAN that encapsulates in an unifying fashion software-based QoS components (mechanisms, algorithms, services), proposed in the literature. To show the usefulness and correctness of the reference architecture, we present three case studies of end-to-end QoS architectures addressing different QoS requirements such as bandwidth and delay with different approaches such as differentiated services and integrated services. We will give an architectural comparison and performance evaluation of these architectures. We believe the reference QoS architectures can help QoS designers to understand the importance and the complexity of various QoS components during the design phase and thus choose these QoS components appropriately.

In ubiquitous sensor networks, the estimation accuracy of a node location is limited due to the presence of non-line-of-sight (NLOS) paths. To mitigate the NLOS effects, this letter proposes a simple algorithm where NLOS identification is carried out using angle-of-arrival (AOA). Simulation results show that the use of AOA improves NLOS identification rates and location estimation accuracy.

In the area of wireless sensor networks, the efficient spatial query processing based on the locations of sensor nodes is required. Especially, spatial queries on two sensor networks need a distributed spatial join processing among the sensor networks. Because the distributed spatial join processing causes lots of wireless transmissions in accessing sensor nodes of two sensor networks, our goal of this paper is to reduce the wireless transmissions for the energy efficiency of sensor nodes. In this paper, we propose an energy-efficient distributed spatial join algorithm on two heterogeneous sensor networks, which performs in-network spatial join processing. To optimize the in-network processing, we also propose a Grid-based Rectangle tree (GR-tree) and a grid-based approximation function. The GR-tree reduces the wireless transmissions by supporting a distributed spatial search for sensor nodes. The grid-based approximation function reduces the wireless transmissions by reducing the volume of spatial query objects which should be pushed down to sensor nodes. Finally, we compare naive and existing approaches through extensive experiments and clarify our approach's distinguished features.

In this paper, an efficient method is proposed to accurately analyze large-scale power/ground (P/G) networks, where inductive parasitics are modeled with the partial reluctance. The method is based on frequency-domain circuit analysis and the technique of vector fitting, and obtains the time-domain voltage response at given P/G nodes. The frequency-domain circuit equation including partial reluctances is derived, and then solved with the GMRES algorithm with rescaling, preconditioning and recycling techniques. With the merit of sparsified reluctance matrix and iterative solving techniques for the frequency-domain circuit equations, the proposed method is able to handle large-scale P/G networks with complete inductive modeling. Numerical results show that the proposed method is orders of magnitude faster than HSPICE, several times faster than INDUCTWISE, and capable of handling the inductive P/G structures with more than 100,000 wire segments.

An accurate behavioral model of a DAC-embedded opamp (DAC-opamp) is developed for a yield-ensuring LCD column driver design. A lookup table for the V-I curve of the unit differential pair in the DAC-opamp is extracted from a circuit simulation and is later manipulated through a random error insertion. Virtual ground assumption simplifies the output voltage estimation algorithm. The developed behavioral model of a 5-bit DAC-opamp shows good agreement with the circuit level simulation with less than 5% INL difference.

This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.

We propose a moving picture coding by lapped transform and an edge adaptive deblocking filter to reduce the blocking distortion. We apply subband coding (SBC) with lapped transform (LT) and zero pruning set partitioning in hierarchical trees (zpSPIHT) to encode the difference picture. Effective coding using zpSPIHT was achieved by quantizing and pruning the quantized zeros. The blocking distortion caused by block motion compensated prediction is reduced by an edge adaptive deblocking filter. Since the original edges can be detected precisely at the reference picture, an edge adaptive deblocking filter on the predicted picture is very effective. Experimental results show that blocking distortion has been visually reduced at very low bit rate coding and better PSNRs of about 1.0 dB was achieved.

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.

In this paper, a Stochastic Collocation Algorithm combined with Sparse Grid technique (SSCA) is proposed to deal with the periodic steady-state analysis for nonlinear systems with process variations. Compared to the existing approaches, SSCA has several considerable merits. Firstly, compared with the moment-matching parameterized model order reduction (PMOR) which equally treats the circuit response on process variables and frequency parameter by Taylor approximation, SSCA employs Homogeneous Chaos to capture the impact of process variations with exponential convergence rate and adopts Fourier series or Wavelet Bases to model the steady-state behavior in time domain. Secondly, contrary to Stochastic Galerkin Algorithm (SGA), which is efficient for stochastic linear system analysis, the complexity of SSCA is much smaller than that of SGA for nonlinear case. Thirdly, different from Efficient Collocation Method, the heuristic approach which may result in "Rank deficient problem" and "Runge phenomenon," Sparse Grid technique is developed to select the collocation points needed in SSCA in order to reduce the complexity while guaranteing the approximation accuracy. Furthermore, though SSCA is proposed for the stochastic nonlinear steady-state analysis, it can be applied to any other kind of nonlinear system simulation with process variations, such as transient analysis, etc.

Future high-resolution short-range automotive radar will have a higher false alarm probability than the conventional low-resolution radar has. In a high-resolution radar, the reception signal becomes sensitive to the difference between intended and unintended objects. However, automotive radars must distinguish targets from background objects that are the same order of size; it leads to an increase in the false alarm probability. In this paper, a CFAR circuit for obtaining the target mean power, as well as the background mean power, is proposed to reduce the false alarm probability for high-resolution radars working in automotive environments. The proposed method is analytically evaluated with use of the characteristic function method. Spatial correlation is also considered in the evaluation, because the sizes of the both target and background objects approach the dimension of several range cells. Result showed the proposed CFAR with use of two alongside range cells could reduce the ratio of 6.4 dB for an example of an automotive situation.