We fabricated metal-oxide-semiconductor (MOS) devices with Pt/Ta2O5 gate stacks and investigated their electrical and structural properties. As increasing RF magnetron sputter-deposition time of Ta2O5 film, the values of equivalent oxide thickness (EOT) and flat band voltage (VFB) increase whilst the density of interfacial trap (Dit) gradually decreases. The effective metal work function (Φm,eff) of Pt metal gate, extracted from the relations of EOT versus VFB are calculated to be ∼5.29 eV, implying that Fermi-level pinning in Ta2O5 gate dielectric is insignificant.

A small broadband omni-directional printed antenna comprising symmetrically arranged trapezoid elements is investigated for broadband Voltage Standing Wave Ratio (VSWR) and low center frequency characteristics. Two symmetrical trapezoid elements are printed on the bottom side of the substrate and are connected to a small ground plane printed on the same side over two strips. The trapezoid elements and the strips are excited in an electromagnetically coupled manner by the monopole element set between the trapezoid elements. Two resonance characteristics arise because the resonance part changes depending on the frequency, and a broad bandwidth becomes possible. The center frequency can be lowered by changing the shapes of the trapezoid elements. The monopole element length is a very important parameter for impedance matching. The space between the monopole element and the trapezoid elements is an important parameter for the optimization of two resonance characteristics. The proposed antenna is shown to achieve a VSWR bandwidth (≤2) of 28.9%, a low profile, and omni-directional pattern features. The measured and numerical results are in good agreement.

In our previous project, an XML-based authoring tool was provided for teachers to script multimedia teaching material with animated agents, and a stand-alone learning system was designed for students to display the material and interact with animated agents. We also provided evidence that the authoring tool and learning system in computer-assisted learning systems successfully enhances learning performance. The aim of this study is to continue the previous project, to develop a Web-based multimedia learning system that presents materials and an animated agent on a Web browser. The Web-based multimedia learning system can provide an opportunity for students to engage in independent learning or review of school course work. In order to demonstrate the efficiency of this learning system, it was applied to one elementary school. An experimental material, `Road Traffic Safety', was presented in two learning systems: a Web-based PowerPoint learning system and a Web-based multimedia learning system. The experiment was carried out in two classes that had a total of thirty-one 3rd-grade students. The results suggest that using our authoring tool in a Web-based learning system can improve learning, and in particular, enhance learners' problem-solving ability. Students with higher achievement on the post-test showed better comprehension in problem-solving questions. Furthermore, the feedback from the questionnaire surveys show students' learning interest can be fostered when an animated agent is integrated into multimedia teaching materials, and that students prefer to adopt the Web-based multimedia learning system for independent learning after school.

Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 40962160 encoding can be achieved with negligible quality loss. 1616 prediction engine and 88 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 88 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2 k gates and can encode 40962160 video sequences at 60 fps with operation frequency of 332 MHz.

We developed a real-world oriented mobile constellation learning environment. Learners point at a target constellation by gazing through a cylinder with a gyro-sensor under the real starry sky. The system can display information related to the constellation. The system has original exercise functions which are not supported by existing systems or products by other research group or companies. Through experimentation, we evaluated the learning environment to assess its learning effects.

Linear discriminant analysis (LDA) is one of the well-known schemes for feature extraction and dimensionality reduction of labeled data. Recently, two-dimensional LDA (2DLDA) for matrices such as images has been reformulated into symmetric 2DLDA (S2DLDA), which is solved by an iterative algorithm. In this paper, we propose a non-iterative S2DLDA and experimentally show that the proposed method achieves comparable classification accuracy with the conventional S2DLDA, while the proposed method is computationally more efficient than the conventional S2DLDA.

One high profile intra predictor generation engine is proposed in this paper. Firstly, hardware level algorithm optimization for intra 88 (I8MB) mode is introduced. The original candidate pixels for generating prediction samples of I8MB are replaced with boundary pixels of intra 44 (I4MB) blocks. Based on this adoption, full data reuse between predictors of I4MB and filtered samples of I8MB can be achieved with almost no quality loss. Secondly, one lossless two-44-block based parallel predictor generation flow is proposed. The original predictor generation flow is optimized from 16 stages to 10 stages for I4MB and Intra 1616 (I16MB), which saves 37.5% processing cycles. For I8MB, similar methodology with different processing order of 44 scaled blocks is introduced. Thirdly, fully utilized hardwired engines for I4MB, I16MB and I8MB are proposed in this paper. Except DC (direct current) and plane modes, full data reuse among all intra modes of high profile can be achieved. Fourthly, for DC mode, one combined predictor generation process is introduced and predictor generation of I16MB's DC mode is merged into the process of I4MB's DC mode. Moreover, by configuring proposed hardwired engines, predictor generation of I16MB's plane mode and chrominance plane mode can be accomplished with only 50% cycles of original design. Totally, when compared with original full-mode design and latest dynamic mode reused design, the proposed predictor generation engine can achieve 89.5% and 73.2% saving of processing cycles, respectively. Synthesized by TSMC 0.18 µm technology under worst work conditions (1.62 V, 125°C), with 380 MHz and 37.2 k gates, the proposed design can handle real-time high profile intra predictor generation of Super Hi-Vision 4 k4 k@60 fps. The maximum work frequency of our design under worst condition is 468 MHz.

Dicode partial response signaling system over inductively-coupled channel has been developed to achieve higher data rate than self-resonant frequencies of inductors. The developed system operates at five times higher data rates than conventional systems with the same inductor. A current-mode equalization in the transmitter designed in a 90-nm CMOS successfully reshapes waveforms to obtain dicode signals at the receiver. For a 5-Gb/s signaling through the coupled inductors with a 120-µm diameter and a 120-µm distance, 20-mV eye opening was observed. The power consumption value of the transmitter was 58 mW at the 5-Gb/s operation.

Internet group-based application layer services such as the overlay networks and P2P systems can benefit from end-to-end network status information. An efficient and accurate bandwidth measurement technique plays an important role in acquiring this information. We propose an end-to-end bottleneck link capacity measurement technique that utilizes path signatures combined with graphical analyses. This feature reduces the probe overhead and decreases the convergence time. We used ns-2 simulations and actual Internet measurements, which resulted in a high level of accuracy and a short probe time with low overhead.

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing. However, the ability of previous X-filling methods to reduce launch switching activity may be unsatisfactory, due to low effect (insufficient and global-only reduction) and/or low scalability (long CPU time). This paper addresses this reduction quality problem with a novel GA (Genetic Algorithm) based X-filling method, called GA-fill. Its goals are (1) to achieve both effectiveness and scalability in a more balanced manner and (2) to make the reduction effect of launch switching activity more concentrated on critical areas that have higher impact on IR-drop-induced yield loss. Evaluation experiments are being conducted on both benchmark and industrial circuits, and the results have demonstrated the usefulness of GA-fill.

The Medium Access Control (MAC) protocol that uses non-overlapping multiple channels, called the multi-channel MAC protocol, was proposed in order to increase the capacity of ad hoc networks. Since the number of packet interfaces on each node is less than the number of channels in ad hoc networks in general, the node needs to select a suitable channel for data transmission. This means that the multi-channel MAC protocol must be provided with a good channel selection algorithm. In this paper, we design a channel selection algorithm called Conditionally Randomized Channel Selection (CRCS) based on Extended Receiver Directed Transmission (xRDT) protocol that only uses one packet interface. Briefly, CRCS uses the acitve channel for data transmission until the amount of data packets reaches a threshold, at which point it selects one of the available channels other than the active channel. Although CRCS is a very simple channel selection algorithm, by using network simulator we find that CRCS is effective to increase the capacity of ad hoc networks and to keep the load balance of all channels compared to the other channel selection algorithms.

This paper presents an improved Gini-Index algorithm to correct feature-selection bias in text classification. Gini-Index has been used as a split measure for choosing the most appropriate splitting attribute in decision tree. Recently, an improved Gini-Index algorithm for feature selection, designed for text categorization and based on Gini-Index theory, was introduced, and it has proved to be better than the other methods. However, we found that the Gini-Index still shows a feature selection bias in text classification, specifically for unbalanced datasets having a huge number of features. The feature selection bias of the Gini-Index in feature selection is shown in three ways: 1) the Gini values of low-frequency features are low (on purity measure) overall, irrespective of the distribution of features among classes, 2) for high-frequency features, the Gini values are always relatively high and 3) for specific features belonging to large classes, the Gini values are relatively lower than those belonging to small classes. Therefore, to correct that bias and improve feature selection in text classification using Gini-Index, we propose an improved Gini-Index (I-GI) algorithm with three reformulated Gini-Index expressions. In the present study, we used global dimensionality reduction (DR) and local DR to measure the goodness of features in feature selections. In experimental results for the I-GI algorithm, we obtained unbiased feature values and eliminated many irrelevant general features while retaining many specific features. Furthermore, we could improve the overall classification performances when we used the local DR method. The total averages of the classification performance were increased by 19.4 %, 15.9 %, 3.3 %, 2.8 % and 2.9 % (kNN) in Micro-F1, 14 %, 9.8 %, 9.2 %, 3.5 % and 4.3 % (SVM) in Micro-F1, 20 %, 16.9 %, 2.8 %, 3.6 % and 3.1 % (kNN) in Macro-F1, 16.3 %, 14 %, 7.1 %, 4.4 %, 6.3 % (SVM) in Macro-F1, compared with tf*idf, χ2, Information Gain, Odds Ratio and the existing Gini-Index methods according to each classifier.

In this paper, an adaptive block-based text line extraction algorithm is proposed. Three global and two local parameters are defined to adapt the method to various handwritings in different languages. A document image is segmented into several overlapping blocks. The skew of each block is estimated. Text block is de-skewed by using the estimated skew angle. Text regions are detected in the de-skewed text block. A number of data points are extracted from the detected text regions in each block. These data points are used to estimate the paths of text lines. By thinning the background of the image including text line paths, text line boundaries or separators are estimated. Furthermore, an algorithm is proposed to assign to the extracted text lines the connected components which have intersections with the estimated separators. Extensive experiments on different standard datasets in various languages demonstrate that the proposed algorithm outperforms previous methods.

We built a 12.4 mm12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.

In order to realize multi-service in TDS-OFDM system, a novel multiplexing scheme based on space time block code is proposed along with the corresponding demultiplexing method with low complexity. Simulations show the presented scheme can not only achieve full diversity gain, but also effectively improve the system capacity.

This paper shows a fast estimation method of very low error rate of low-density parity-check (LDPC) codes. No analytical tool is available to evaluate performance of LDPC codes, and the traditional Monte Carlo simulation methods can not estimate the low error rate of LDPC codes due to the limitation of time. To conquer this problem, we propose another simulation method which is based on the optimal simulation probability density function (PDF). The proposed simulation PDF can also avoid the dependency between the simulation time and the number of dominant trapping sets, which is the problem of some fast simulation methods based on the error event simulation method. Additionally, we show some numerical examples to demonstrate the effectiveness of the proposed method. The simulation time of the proposed method is reduced to almost less than 1/10 of that of Cole et al.'s method under the condition of the same accuracy of the estimator.

Repetitive synchronization sequences in the time domain can be used to estimate Carrier Frequency Offset (CFO). The Un-Guarded Maximum Likelihood (UGML) estimator and Guarded ML (GML) estimator of CFO in the frequency selective channel are proposed in this paper. The results of theoretical analysis show that the UGML estimator is hard to implement if the channel response is not known while the GML estimator can be easily implemented due to inserted guard sequences. The guard sequences can be easily implemented as Cyclic Prefix (CP) in OFDM system. Therefore, the UGML estimator is only suitable for the systems where the channel response can be predetermined. This paper also gives a comparison with the existing CFO estimator. Theoretical and simulation results show that both the proposed estimators outperform the existing estimator.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold timing constraint, as well as the setup timing constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup timing constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold timing constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold timing constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by Backward-Data-Direction (BDD) clocking. One of the drawbacks of the proposed register assignment is the increase in the number of required registers. After the formulation of this new register minimization problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by BDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.

This paper discusses a dual-stage detection scheme composed of coarse detection stage and refined detection stage for the continuous detection operation of Ultra-Wideband (UWB) detect and avoid (DAA). The threshold factor for the probability of indefinite detection is first proposed and defined to combine the two stages. The proposed scheme focuses on the integration of two different detection schemes with different complexities in order to reduce total computational complexity. A Single-carrier Frequency Division Multiple Access (SC-FDMA) uplink system operating in a Time Division Duplex (TDD) mode is utilized to evaluate the proposed detection scheme. Simulation results indicate that the proposed scheme can make a tradeoff between the detection performance and the computational complexity by setting the probability of indefinite detection.

This paper presents a syntax-based framework for gap resolution in analytic languages. CCG, reputable for dealing with deletion under coordination, is extended with a memory mechanism similar to the slot-and-filler mechanism, resulting in a wider coverage of syntactic gaps patterns. Though our grammar formalism is more expressive than the canonical CCG, its generative power is bounded by Partially Linear Indexed Grammar. Despite the spurious ambiguity originated from the memory mechanism, we also show that its probabilistic parsing is feasible by using the dual decomposition algorithm.