This work investigates the effect of channel estimation error on the average secrecy outage capacity of dual selection in the presence of multiple eavesdroppers. The dual selection selects a transmit antenna of Alice and Bob (i.e., user terminal) which provide the best received signal to noise ratio (SNR) using channel state information from every user terminals. Using Gaussian approximation, this paper obtains the tight analytical expression of the dual selection for the average secrecy outage capacity over channel estimation error and multiple eavesdroppers. Using asymptotic analysis, this work quantifies the high SNR power offset and the high SNR slope for the average secrecy outage capacity at high SNR.

Given a graph G=(V, E), where V and E are vertex and edge sets of G, and a subset VNT of vertices called a non-terminal set, a spanning tree with a non-terminal set VNT, denoted by STNT, is a connected and acyclic spanning subgraph of G that contains all vertices of V where each vertex in a non-terminal set is not a leaf. On general graphs, the problem of finding an STNT of G is known to be NP-hard. In this paper, we show that if G is a circular-arc graph then finding an STNT of G is polynomially solvable with respect to the number of vertices.

Nowadays, a rapid increase of demand on high-performance computation causes the enthusiastic research activities regarding massively parallel systems. An interconnection network in a massively parallel system interconnects a huge number of processing elements so that they can cooperate to process tasks by communicating among others. By regarding a processing element and a link between a pair of processing elements as a node and an edge, respectively, many problems with respect to communication and/or routing in an interconnection network are reducible to the problems in the graph theory. For interconnection networks of the massively parallel systems, many topologies have been proposed so far. The hypercube is a very popular topology and it has many variants. The bicube is a such topology and it can interconnect the same number of nodes with the same degree as the hypercube while its diameter is almost half of that of the hypercube. In addition, the bicube keeps the node-symmetric property. Hence, we focus on the bicube and propose an algorithm that gives a minimal or shortest path between an arbitrary pair of nodes. We give a proof of correctness of the algorithm and demonstrate its execution.

Cryptocurrency abuse has become a critical problem. Due to the anonymous nature of cryptocurrency, criminals commonly adopt cryptocurrency for trading drugs and deceiving people without revealing their identities. Despite its significance and severity, only few works have studied how cryptocurrency has been abused in the real world, and they only provide some limited measurement results. Thus, to provide a more in-depth understanding on the cryptocurrency abuse cases, we present a large-scale analysis on various Bitcoin abuse types using 200,507 real-world reports collected by victims from 214 countries. We scrutinize observable abuse trends, which are closely related to real-world incidents, to understand the causality of the abuses. Furthermore, we investigate the semantics of various cryptocurrency abuse types to show that several abuse types overlap in meaning and to provide valuable insight into the public dataset. In addition, we delve into abuse channels to identify which widely-known platforms can be maliciously deployed by abusers following the COVID-19 pandemic outbreak. Consequently, we demonstrate the polarization property of Bitcoin addresses practically utilized on transactions, and confirm the possible usage of public report data for providing clues to track cyber threats. We expect that this research on Bitcoin abuse can empirically reach victims more effectively than cybercrime, which is subject to professional investigation.

The resistor variation can severely affect current reference sources, which may vary up to ±40% in scaled CMOS processes. In addition, such variations make the opamp design challenging and increase the design margin, impacting power consumption. This paper proposes a Time-Based Current Source (TBCS): a robust and process-scalable reference current source suitable for switched-capacitor (SC) circuits. We construct a delay-locked-loop (DLL) to lock the current-starved inverter with the reference clock, enabling the use of the settled current directly as a reference current. Since the load capacitors determine the delay, the generated current is decoupled from resistor values and enables a robust reference current source. The prototype TBCS fabricated in 28nm CMOS achieved a minimal area of 1200um2. The current variation is suppressed to half compared to BGR based current sources, confirmed in extensive PVT variation simulations. Moreover, when used as the opamp's bias, TBCS achieves comparable opamp GBW to an ideal current source.

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert malicious circuits, called hardware Trojans, into their products, developing an effective hardware-Trojan detection method is strongly required. In this paper, we propose 25 hardware-Trojan features focusing on the structure of trigger circuits for machine-learning-based hardware-Trojan detection. Combining the proposed features into 11 existing hardware-Trojan features, we totally utilize 36 hardware-Trojan features for classification. Then we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on a random-forest classifier. The experimental results demonstrate that the average true positive rate (TPR) becomes 64.2% and the average true negative rate (TNR) becomes 100.0%. They improve the average TPR by 14.8 points while keeping the average TNR compared to existing state-of-the-art methods. In particular, the proposed method successfully finds out Trojan nets in several benchmark circuits, which are not found by the existing method.

A robust saliency detection approach for images with a complex background is proposed. The absorbing Markov chain integrating low-level, mid-level and high-level cues dynamically evolves by using the similarity between pixels to detect saliency objects. The experimental results show that the proposed algorithm has advantages in saliency detection, especially for images with a chaotic background or low contrast.

In this paper, we study the number of failed components in a consecutive-k-out-of-n:G system. The distributions and expected values of the number of failed components when system is failed or working at a particular time t are evaluated. We also apply them to the optimization problems concerned with the optimal number of components and the optimal replacement time. Finally, we present the illustrative examples for the expected number of failed components and give the numerical results for the optimization problems.

A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic device. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, and several low-latency AQFP logic gates have been demonstrated. In delay-line clocking, the latency between adjacent excitation phases is determined by the propagation delay of excitation currents, and thus the rising time of excitation currents should be sufficiently small; otherwise, an AQFP gate can switch before the previous gate is fully excited. This means that delay-line clocking needs high clock frequencies, because typical excitation currents are sinusoidal and the rising time depends on the frequency. However, AQFP circuits need to be tested in a wide frequency range experimentally. Hence, in the present study, we investigate AQFP circuits adopting delay-line clocking with square excitation currents to apply delay-line clocking in a low frequency range. Square excitation currents have shorter rising time than sinusoidal excitation currents and thus enable low frequency operation. We demonstrate an AQFP buffer chain with delay-line clocking using square excitation currents, in which the latency is approximately 20ps per gate, and confirm that the operating margin for the buffer chain is kept sufficiently wide at clock frequencies below 1GHz, whereas in the sinusoidal case the operating margin shrinks below 500MHz. These results indicate that AQFP circuits adopting delay-line clocking can operate in a low frequency range by using square excitation currents.

We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 - 6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.

This study tries to predict date of ear emergence of rice plants, based on cropping records over 25 years. Predicting ear emergence of rice plants is known to be crucial for practicing good harvesting quality, and has long been dependent upon old farmers who acquire skills of intuitive prediction based on their long term experiences. Facing with aging farmers, data driven approach for the prediction have been pursued. Nevertheless, they are not necessarily sufficient in terms of practical use. One of the issue is to adopt weather forecast as the feature so that the predictive performance is varied by the accuracy of the forecast. The other issue is that the performance is varied by region and the regional characteristics have not been used as the features for the prediction. With this background, we propose a feature engineering to quantify hidden regional characteristics as the feature for the prediction. Further the feature is engineered based only on observational data without any forecast. Applying our proposal to the data on the cropping records resulted in sufficient predictive performance, ±2.69days of RMSE.

With the spread of the 5th generation mobile phone, the increase of the output power of PA (power amplifier) has become important, and in recent years, differential amplifiers that can increase the output voltage amplitude for the power supply voltage have been examined from the viewpoint of power synthesis. In the case of a differential PA, in addition to the advantage of voltage amplitude, the load impedance can be set 4 times as much as that of a single-ended PA, which makes it possible to reduce the impact of parasitic resistance. With the study of the differential PA, many transformer matching circuits have been studied in addition to the LC matching circuits that have been widely used in the past. The transformer matching circuit can easily realize the differential-single conversion, and the transformer matching circuit is an indispensable technology in the differential PA. As with the LC matching circuit, widening the bandwidth of the transformer matching circuit is at issue. In this paper, characteristics of basic transformer matching circuits are analyzed by adding input/output shunt capacitance to transformers and the conditions of bandwidth improvement are clarified. In addition, by comparing the FBW (fractional bandwidth) with the LC 2-stage matching circuit, it is shown that the FBW can be competitive.

In the fifth-generation mobile communications system (5G), it is critical to ensure wireless security as well as large-capacity and high-speed communication. To achieve this, a chaos modulation method as an encrypted and channel-coded modulation method in the physical layer is proposed. However, in the conventional chaos modulation method, the decoding complexity increases exponentially with respect to the modulation order. To solve this problem, in this study, a hybrid modulation method that applies quadrature amplitude modulation (QAM) and chaos to reduce the amount of decoding complexity, in which some transmission bits are allocated to QAM while maintaining the encryption for all bits is proposed. In the proposed method, a low-complexity decoding method is constructed by ordering chaos and QAM symbols based on the theory of index modulation. Numerical results show that the proposed method maintains good error-rate performance with reduced decoding complexity and ensures wireless security.

In response to fast charging systems, Silicon Carbide (SiC) power semiconductor devices are of great interest of the automotive power electronics applications as the next generation of fast charging systems require high voltage batteries. For high voltage battery EVs (Electric Vehicles) over 800V, SiC power semiconductor devices are suitable for 3-phase inverters, battery chargers, and isolated DC-DC converters due to their high voltage rating and high efficiency performance. However, SiC-MOSFETs have two characteristics that interfere with high-speed switching and high efficiency performance operations for SiC MOS-FET applications in automotive power electronics systems. One characteristic is the low voltage rating of the gate-source terminal, and the other is the large internal gate-resistance of SiC MOS-FET. The purpose of this work was to evaluate a proposed hybrid gate drive circuit that could ignore the internal gate-resistance and maintain the gate-source terminal stability of the SiC-MOSFET applications. It has been found that the proposed hybrid gate drive circuit can achieve faster and lower loss switching performance than conventional gate drive circuits by using the current source gate drive characteristics. In addition, the proposed gate drive circuit can use the voltage source gate drive characteristics to protect the gate-source terminals despite the low voltage rating of the SiC MOS-FET gate-source terminals.

This paper presents a physical layer wireless device identification method that uses a convolutional neural network (CNN) operating on a quadrant IQ transition image. This work introduces classification and detection tasks in one process. The proposed method can identify IoT wireless devices by exploiting their RF fingerprints, a technology to identify wireless devices by using unique variations in analog signals. We propose a quadrant IQ image technique to reduce the size of CNN while maintaining accuracy. The CNN utilizes the IQ transition image, which image processing cut out into four-part. An over-the-air experiment is performed on six Zigbee wireless devices to confirm the proposed identification method's validity. The measurement results demonstrate that the proposed method can achieve 99% accuracy with the light-weight CNN model with 36,500 weight parameters in serial use and 146,000 in parallel use. Furthermore, the proposed threshold algorithm can verify the authenticity using one classifier and achieved 80% accuracy for further secured wireless communication. This work also introduces the identification of expanded signals with SNR between 10 to 30dB. As a result, at SNR values above 20dB, the proposals achieve classification and detection accuracies of 87% and 80%, respectively.

To sustain and expand the agricultural economy even as its workforce shrinks, the efficiency of farm operations must be improved. One key to efficiency improvement is completely unmanned driving of farm machines, which requires stable monitoring and control of machines from remote sites, a safety system to ensure safe autonomous driving even without manual operations, and precise positioning in not only small farm fields but also wider areas. As possible solutions for those issues, we have developed technologies of wireless network quality prediction, an end-to-end overlay network, machine vision for safety and positioning, network cooperated vehicle control and autonomous tractor control and conducted experiments in actual field environments. Experimental results show that: 1) remote monitoring and control can be seamlessly continued even when connection between the tractor and the remote site needs to be switched across different wireless networks during autonomous driving; 2) the safety of the autonomous driving can automatically be ensured by detecting both the existence of people in front of the unmanned tractor and disturbance of network quality affecting remote monitoring operation; and 3) the unmanned tractor can continue precise autonomous driving even when precise positioning by satellite systems cannot be performed.

Computer networks tend to be subjected to the proliferation of mobile demands, therefore it poses a great challenge to guarantee the quality of network service. For real-time systems, the QoS performance bound analysis for the complex network topology and background traffic in modern networks is often difficult. Network calculus, nevertheless, converts a complex non-linear network system into an analyzable linear system to accomplish more accurate delay bound analysis. The existing network environment contains complex network resource allocation schemes, and delay bound analysis is generally pessimistic, hence it is essential to modify the analysis model to improve the bound accuracy. In this paper, the main research approach is to obtain the measurement results of an actual network by building a measurement environment and the corresponding theoretical results by network calculus. A comparison between measurement data and theoretical results is made for the purpose of clarifying the scheme of bandwidth scheduling. The measurement results and theoretical analysis results are verified and corrected, in order to propose an accurate per-flow end-to-end delay bound analytic model for a large-scale scheduling network. On this basis, the instructional significance of the analysis results for the engineering construction is discussed.