Research on wireless power transmission technology is being actively conducted, and studies on spatial transmission methods such as SSPS are currently underway for applications such as power transfer to the upper part of steel towers and power transfer to flying objects such as drones. To enable such applications, it is necessary to examine the configuration of the power-transfer and power-receiving antennas and to improve the RF-DC conversion efficiency (hereinafter referred to as conversion efficiency) of the rectifier circuit on the power-receiving antenna. To improve the conversion efficiency, various methods that utilize full-wave rectification rather than half-wave rectification have been proposed. However, these come with problems such as a complicated circuit structure, the need for additional capacitors, the selection of components at high frequencies, and a reduction in mounting yield. In this paper, we propose a method to improve the conversion efficiency by loading a high-impedance microstrip line as a feedback line in part of the rectifier circuit. We analyzed a class-F rectifier circuit using circuit analysis software and found that the conversion efficiency of the conventional configuration was 54.2%, but the proposed configuration was 69.3%. We also analyzed a measuring circuit made with a discrete configuration in the 5.8-GHz band and found that the conversion efficiency was 74.7% at 24dBm input.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

Standard neural machine translation (NMT) is on the assumption that the document-level context is independent. Most existing document-level NMT approaches are satisfied with a smattering sense of global document-level information, while this work focuses on exploiting detailed document-level context in terms of a memory network. The capacity of the memory network that detecting the most relevant part of the current sentence from memory renders a natural solution to model the rich document-level context. In this work, the proposed document-aware memory network is implemented to enhance the Transformer NMT baseline. Experiments on several tasks show that the proposed method significantly improves the NMT performance over strong Transformer baselines and other related studies.

Receiver selective opening (RSO) attack for public key encryption (PKE) captures a situation where one sender sends messages to multiple receivers, an adversary can corrupt a set of receivers and get their messages and secret keys. Security against RSO attack for a PKE scheme ensures confidentiality of other uncorrupted receivers' ciphertexts. Among all of the RSO security notions, simulation-based RSO security against chosen ciphertext attack (SIM-RSO-CCA security) is the strongest notion. In this paper, we explore constructions of SIM-RSO-CCA secure PKE from various computational assumptions. Toward this goal, we show that a SIM-RSO-CCA secure PKE scheme can be constructed based on an IND-CPA secure PKE scheme and a designated-verifier non-interactive zero-knowledge (DV-NIZK) argument satisfying one-time simulation soundness. Moreover, we give the first construction of DV-NIZK argument satisfying one-time simulation soundness. Consequently, through our generic construction, we obtain the first SIM-RSO-CCA secure PKE scheme under the computational Diffie-Hellman (CDH) or learning parity with noise (LPN) assumption.

Predicting the malfunction timing of wind turbines is essential for maintaining the high profitability of the wind power generation business. Machine learning methods have been studied using condition monitoring system data, such as vibration data, and supervisory control and data acquisition (SCADA) data, to detect and predict anomalies in wind turbines automatically. Autoencoder-based techniques have attracted significant interest in the detection or prediction of anomalies through unsupervised learning, in which the anomaly pattern is unknown. Although autoencoder-based techniques have been proven to detect anomalies effectively using relatively stable SCADA data, they perform poorly in the case of deteriorated SCADA data. In this letter, we propose a power-curve filtering method, which is a preprocessing technique used before the application of an autoencoder-based technique, to mitigate the dirtiness of SCADA data and improve the prediction performance of wind turbine degradation. We have evaluated its performance using SCADA data obtained from a real wind-farm.

Air traffic management (ATM) systems around the world are being modernized to accommodate shifts towards performance- and trajectory-based operations. These shifts will require new indices for safety, efficiency and complexity. The authors have been developing an index for evaluating air traffic control (ATC) difficulty that utilizes the relative positions and velocity vectors of aircraft pairs as input data. Prior to practical application of the index, it is necessary to understand the effects of input data error, i.e. errors in the positions and velocities of a pair of aircraft, on the estimated difficulty value. Two sensitivity analyses were therefore performed for a pair of aircraft cruising at constant speeds on intersecting linear tracks at the same altitude. Sensitivity analysis examines how uncertainty in inputs relates to uncertainty in outputs. Firstly, an analysis of propagation error was carried out. The formula of the propagation error at a certain point was derived based on the assumed input error, and the distribution of propagation error was investigated for all possible situations and compared with the distribution of difficulty values to clarify its characteristics. Secondly, a sensitivity analysis based on variance was carried out that evaluated the effect of each input parameter using a conditional variance value called the Sobol indices. Using a Monte Carlo method, we investigated the effect of each input parameter on the calculated difficulty value for all possible situations of aircraft pairs on intersecting trajectories. As a result, it was found that the parameter that most affects the difficulty value is the intersection angle of the trajectories.

Isogeny-based cryptography, such as commutative supersingular isogeny Diffie-Hellman (CSIDH), have been shown to be promising candidates for post-quantum cryptography. However, their speeds have remained unremarkable. This study focuses on computing odd-degree isogeny between Montgomery curves, which is a dominant computation in CSIDH. Our proposed “2-ADD-Skip method” technique reduces the required number of points to be computed during isogeny computation. A novel algorithm for isogeny computation is also proposed to efficiently utilize the 2-ADD-Skip method. Our proposed algorithm with the optimized parameter reduces computational cost by approximately 12% compared with the algorithm proposed by Meyer and Reith. Further, individual experiments for each degree of isogeny ℓ show that the proposed algorithm is the fastest for 19≤ℓ≤373 among previous studies focusing on isogeny computation including the Õ(√ℓ) algorithm proposed by Bernstein et al. The experimental results also show that the proposed algorithm achieves the fastest on CSIDH-512. For CSIDH-1024, the proposed algorithm is faster than the algorithm by Meyer and Reith although it is slower than the algorithm by Bernstein et al.

HTTP Distributed Denial of Service (DDoS) flooding attack aims to deplete the connection resources of a targeted web server by transmitting a massive amount of HTTP request packets using botnets. This type of attack seriously deteriorates the service quality of the web server by tying up its connection resources and uselessly holds up lots of network resources like link capacity and switching capability. This paper proposes a defense method for mitigating HTTP DDoS flooding attack based on software-defined networking (SDN). It is demonstrated in this paper that the proposed method can effectively defend the web server and preserve network resources against HTTP DDoS flooding attacks.

This paper presents the average block error rate (BLER) performance of circular 32QAM and 64QAM schemes employing a frequency domain equalizer (FDE) for discrete Fourier transform (DFT)-precoded orthogonal frequency division multiplexing (OFDM) in multipath Rayleigh fading channels. The circular QAM scheme has an advantageous feature in that the fluctuation in the amplitude component is smaller than that for the cross or rectangular QAM scheme. Hence, focusing on the actual received signal-to-noise power ratio (SNR) taking into account a realistic peak-to-average power ratio (PAPR) measure called the cubic metric (CM), we compare the average BLER of the circular 32QAM and 64QAM schemes with those of cross 32QAM and rectangular 64QAM schemes, respectively. We investigate the theoretical throughput of various circular 32QAM and 64QAM schemes based on mutual information from the viewpoint of the minimum Euclidean distance. Link-level simulation results show that the circular 32QAM and 64QAM schemes with independent bit mapping for the phase and amplitude modulations achieves a lower required average received SNR considering the CM than that with the minimum Euclidean distance but with composite mapping of the phase and amplitude modulations. Through extensive link-level simulations, we show the potential benefit of the circular 32QAM and 64QAM schemes in terms of reducing the required average received SNR considering the CM that satisfies the target average BLER compared to the cross 32QAM or rectangular 64QAM scheme.

We provide a formal proof for the indifferentiability of SKINNY-HASH internal function from a random oracle. SKINNY-HASH is a family of sponge-based hash functions that use functions (instead of permutations) as primitives, and it was selected as one of the second round candidates of the NIST lightweight cryptography competition. Its internal function is constructed from the tweakable block cipher SKINNY. The construction of the internal function is very simple and the designers claim n-bit security, where n is the block length of SKINNY. However, a formal security proof of this claim is not given in the original specification of SKINNY-HASH. In this paper, we formally prove that the internal function of SKINNY-HASH has n-bit security, i.e., it is indifferentiable from a random oracle up to O(2n) queries, substantiating the security claim of the designers.

In March 2020, the 5th generation mobile communication system (5G) was launched in Japan. Frequency bands of 3.7GHz, 4.5GHz and 28GHz were allocated for 5G services, and the 5G use cases fall into three broad categories: Enhanced Mobile Broadband (eMBB), Massive Machine Type Communication (mMTC) and Ultra-Reliable Low Latency Communication (URLLC). The use cases and services that take advantage of the characteristics of each category are expected to be put to practical use, and experiments of practical use are underway. This paper introduces and demonstrates a touchless gate that can identify, authenticate and allow passage through the gate by using these features and 5G beam tracking to estimate location by taking advantage of the low latency of 5G and the straightness of the 28GHz band radio wave and its resistance to spreading. Since position estimation error due to reflected waves and other factors has been a problem, we implement an algorithm that tracks the beam and estimates the user's line of movement, and by using an infrared sensor, we made it possible to identify the gate through which the user passes with high probability. We confirmed that the 5G touchless gate is feasible for gate passage. In addition, we demonstrate that a new service based on high-speed high-capacity communication is possible at gate passage by taking advantage of the wide bandwidth of the 28GHz band. Furthermore, as a use case study of the 5G touchless gate, we conducted a joint experiment with an airline company.

This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.

The microfabrication technique based on synchrotron radiation (SR) direct etching process has recently been applied to construct PTFE microstructures. This paper proposes a PTFE substrate integrated waveguide (PTFE SIW). It is expected that the PTFE SIW contributes to the improvement of the structural strength. A rectangular through-hole is introduced taking the advantage of the SR direct etching process. First, a PTFE SIW for the Q-band is designed. Then, a cruciform 3-dB directional coupler consisting of the PTFE SIW is designed and fabricated by the SR direct etching process. The validity of the PTFE SIW coupler is confirmed by measuring the frequency characteristics of the S-parameters. The mechanical strength of the PTFE SIW and the peeling strength of its Au film are also additionally investigated.

A universal interconnection network implements arbitrary interconnections among n terminals. This paper considers a problem to realize such a network using contact switches. When n=2, it can be implemented with a single switch. The number of different connections among n terminals is given by the Bell number B(n). The Bell number shows the total number of methods to partition n distinct elements. For n=2, 3, 4, 5 and 6, the corresponding Bell numbers are 2, 5, 15, 52, and 203, respectively. This paper shows a method to realize an n terminal universal interconnection network with $rac {3}{8}(n^2-1)$ contact switches when n=2m+1≥5, and $rac {n}{8}(3n+2)$ contact switches, when n=2m≥6. Also, it shows that a lower bound on the number of contact switches to realize an n-terminal universal interconnection network is ⌈log 2B(n)⌉, where B(n) is the Bell number.

Data parallelism is the dominant method used to train deep learning (DL) models on High-Performance Computing systems such as large-scale GPU clusters. When training a DL model on a large number of nodes, inter-node communication becomes bottle-neck due to its relatively higher latency and lower link bandwidth (than intra-node communication). Although some communication techniques have been proposed to cope with this problem, all of these approaches target to deal with the large message size issue while diminishing the effect of the limitation of the inter-node network. In this study, we investigate the benefit of increasing inter-node link bandwidth by using hybrid switching systems, i.e., Electrical Packet Switching and Optical Circuit Switching. We found that the typical data-transfer of synchronous data-parallelism training is long-lived and rarely changed that can be speed-up with optical switching. Simulation results on the Simgrid simulator show that our approach speed-up the training time of deep learning applications, especially in a large-scale manner.

In this paper, we propose a design method for a diplexer using a surface acoustic wave (SAW) filter, a multilayer ceramic filter, chip inductors, and chip capacitors. A controllable transmission zero can be created in the stopband by designing matching circuits based on the out-of-band characteristics of the SAW filter using this method. The proposed method can achieve good attenuation performance and a compact size because it does not use an additional resonator for creating the controllable transmission zero and the matching circuits are composed of only five components. A diplexer is designed for 2.4 GHz wireless systems and a global positioning system receiver using the proposed method. It is compact (8.0 mm × 8.0 mm), and the measurement results indicate good attenuation performance with the controllable transmission zero.

Cache prefetching technique brings huge benefits to performance improvement, but it comes at the cost of microarchitectural security in processors. In this letter, we deep dive into internal workings of a DCUIP prefetcher, which is one of prefetchers equipped in Intel processors. We discover that a DCUIP table is shared among different execution contexts in hyperthreading-enabled processors, which leads to another microarchitectural vulnerability. By exploiting the vulnerability, we propose a DCUIP poisoning attack. We demonstrate an AES encryption key can be extracted from an AES-NI implementation by mounting the proposed attack.

This study presents a formal verification method for Galois-field (GF) arithmetic circuits with the characteristics of more than two values. The proposed method formally verifies the correctness of circuit functionality (i.e., the input-output relations given as GF-polynomials) by checking the equivalence between a specification and a gate-level netlist. We represent a netlist using simultaneous algebraic equations and solve them based on a novel polynomial reduction method that can be efficiently applied to arithmetic over extension fields $mathbb{F}_{p^m}$, where the characteristic p is larger than two. By using the reverse topological term order to derive the Gröbner basis, our method can complete the verification, even when a target circuit includes bugs. In addition, we introduce an extension of the Galois-Field binary moment diagrams to perform the polynomial reductions faster. Our experimental results show that the proposed method can efficiently verify practical $mathbb{F}_{p^m}$ arithmetic circuits, including those used in modern cryptography. Moreover, we demonstrate that the extended polynomial reduction technique can enable verification that is up to approximately five times faster than the original one.

A new threshold circuit technique is proposed for a vibration sensing circuit that operates at a nanowatt power level. The sensing circuits that use sample-and-hold require a clock signal, and they consume power to generate a signal. In the use of a Schmitt trigger circuit that does not use a clock signal, a sink current flows when thresholding the analog signal output. The requirements for millimeter-sized wireless sensor nodes are an average power on the order of a nanowatt and a signal transition time of less than 1 ms. To meet these requirements, our circuit limits the sink current with a nanoampere-level current source. The chattering caused by current limiting is suppressed by feeding back the change in output voltage to the limiting current. The increase in the signal transition time that is caused by current limiting is reduced by accelerating the discharge of the load capacitance. For a test chip fabricated in the 0.35-µm CMOS process, the proposed threshold circuits operate without chattering and the average powers are 0.7-3 nW. The signal transition times are estimated in a circuit simulation to be 65-97 µs. The proposed circuit has 1/150th the power-delay product with no time interval of the sensing operation under the condition that the time interval is 1s. These results indicate that, the proposed threshold circuits are suitable for vibration sensing in millimeter-sized wireless sensor nodes.

Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.