Stochastic Computing (SC) allows additions and multiplications to be realized with lower power than the conventional binary operations if we admit some errors. However, for many complex functions which cannot be realized by only additions and multiplications, we do not know a generic efficient method to calculate a function by using an SC circuit; it is necessary to realize an SC circuit by using a generic method such as polynomial approximation methods for such a function, which may lose the advantage of SC. Thus, there have been many researches to consider efficient SC realization for specific functions; an efficient SC square root circuit with a feedback circuit was proposed by D. Wu et al. recently. This paper generalizes the SC square root circuit with a feedback circuit; we identify a situation when we can implement a function efficiently by an SC circuit with a feedback circuit. As examples of our generalization, we propose SC circuits to calculate the n-th root calculation and division. We also show our analysis on the accuracy of our SC circuits and the hardware costs; our results show the effectiveness of our method compared to the conventional SC designs; our framework may be able to implement a SC circuit that is better than the existing methods in terms of the hardware cost or the calculation error.

Emerging data-intensive services in distribution grid impose requirements of high-concurrency access for massive internet of things (IoT) devices. However, the lack of effective high-concurrency access management results in severe performance degradation. To address this challenge, we propose a cloud-edge-device collaborative high-concurrency access management algorithm based on multi-timescale joint optimization of channel pre-allocation and load balancing degree. We formulate an optimization problem to minimize the weighted sum of edge-cloud load balancing degree and queuing delay under the constraint of access success rate. The problem is decomposed into a large-timescale channel pre-allocation subproblem solved by the device-edge collaborative access priority scoring mechanism, and a small-timescale data access control subproblem solved by the discounted empirical matching mechanism (DEM) with the perception of high-concurrency number and queue backlog. Particularly, information uncertainty caused by externalities is tackled by exploiting discounted empirical performance which accurately captures the performance influence of historical time points on present preference value. Simulation results demonstrate the effectiveness of the proposed algorithm in reducing edge-cloud load balancing degree and queuing delay.

In this work, the core size estimation technique of magnetic nanoparticles (MNPs) using the static magnetization curve obtained from a high-Tc SQUID magnetometer and a metaheuristic inversion technique based on the Particle Swarm Optimizer (PSO) algorithm is presented. The high-Tc SQUID magnetometer is constructed from a high-Tc SQUID sensor coupled by a flux transformer to sense the modulated magnetization signal from a sample. The magnetization signal is modulated by the lateral vibration of the sample on top of a planar differential detection coil of the flux transformer. A pair of primary and excitation coils are utilized to apply an excitation field parallel to the sensitive axis of the detection coil. Using the high-Tc SQUID magnetometer, the magnetization curve of a commercial MNP sample (Resovist) was measured in a logarithmic scale of the excitation field. The PSO inverse technique is then applied to the magnetization curve to construct the magnetic moment distribution. A multimodal normalized log-normal distribution was used in the minimization of the objective function of the PSO inversion technique, and a modification of the PSO search region is proposed to improve the exploration and exploitation of the PSO particles. As a result, a good agreement on the Resovist magnetic core size was obtained between the proposed technique and the non-negative least square (NNLS) inversion technique. The estimated core sizes of 8.0484 nm and 20.3018 nm agreed well with the values reported in the literature using the commercial low-Tc SQUID magnetometer with the SVD and NNLS inversion techniques. Compared to the NNLS inversion technique, the PSO inversion technique had merits in exploring an optimal core size distribution freely without being regularized by a parameter and facilitating an easy peak position determination owing to the smoothness of the constructed distribution. The combination of the high-Tc SQUID magnetometer and the PSO-based reconstruction technique offers a powerful approach for characterizing the MNP core size distribution, and further improvements can be expected from the recent state-of-the-art optimization algorithm to optimize further the computation time and the best objective function value.

Despite the appealing advantages of reconfigurable intelligent surfaces (RIS) aided mmWave communications, there remain practical issues that need to be addressed before the large-scale deployment of RISs in future wireless networks. In this study, we jointly consider the non-neglectable practical issues in a multi-RIS-aided mmWave system, which can significantly affect the secrecy performance, including the high computational complexity, imperfect channel state information (CSI), and finite resolution of phase shifters. To solve this non-convex challenging stochastic optimization problem, we propose a robust and low-complexity algorithm to maximize the achievable secrete rate. Specially, by combining the benefits of fractional programming and the stochastic successive convex approximation techniques, we transform the joint optimization problem into some convex ones and solve them sub-optimally. The theoretical analysis and simulation results demonstrate that the proposed algorithms could mitigate the joint negative effects of practical issues and yielded a tradeoff between secure performance and complexity/overhead outperforming non-robust benchmarks, which increases the robustness and flexibility of multiple RIS deployments in future wireless networks.

Security-related issues have become more significant due to the proliferation of IT. Collating security-related information in a database improves security. For example, Common Vulnerabilities and Exposures (CVE) is a security knowledge repository containing descriptions of vulnerabilities about software or source code. Although the descriptions include various entities, there is not a uniform entity structure, making security analysis difficult using individual entities. Developing a consistent entity structure will enhance the security field. Herein we propose a method to automatically label select entities from CVE descriptions by applying the Named Entity Recognition (NER) technique. We manually labeled 3287 CVE descriptions and conducted experiments using a machine learning model called BERT to compare the proposed method to labeling with regular expressions. Machine learning using the proposed method significantly improves the labeling accuracy. It has an f1 score of about 0.93, precision of about 0.91, and recall of about 0.95, demonstrating that our method has potential to automatically label select entities from CVE descriptions.

An efficient optical power splitter constructed by a metal-dielectric-metal plasmonic waveguide with a resonator structure has been analyzed. The method of solution is the finite difference time domain (FD-TD) method with the piecewise linear recursive convolution (PLRC) method. The resonator structure consists of input/output waveguides and a narrow waveguide with a T-junction. The power splitter with the resonator structure is expressed by an equivalent transmission-line circuit. We can find that the transmittance and reflectance calculated by the FD-TD method and the equivalent circuit are matched when the difference in width between the input/output waveguides and the narrow waveguide is small. It is also shown that the transmission wavelength can be adjusted by changing the narrow waveguide lengths that satisfy the impedance matching condition in the equivalent circuit.

Cloud gaming systems allow users to play games that require high-performance computational capability on their mobile devices at any location. However, playing games through cloud gaming systems increases the Round-Trip Time (RTT) due to increased network delay. To simulate a local gaming experience for cloud users, we must minimize RTTs, which include network delays. The speculative video transmission pre-generates and encodes video frames corresponding to all possible user inputs and sends them to the user before the user’s input. The speculative video transmission mitigates the network, whereas a simple solution significantly increases the video traffic. This paper proposes tile-wise delta detection for traffic reduction of speculative video transmission. More specifically, the proposed method determines a reference video frame from the generated video frames and divides the reference video frame into multiple tiles. We calculate the similarity between each tile of the reference video frame and other video frames based on a hash function. Based on calculated similarity, we determine redundant tiles and do not transmit them to reduce traffic volume in minimal processing time without implementing a high compression ratio video compression technique. Evaluations using commercial games showed that the proposed method reduced 40-50% in traffic volume when the SSIM index was around 0.98 in certain genres, compared with the speculative video transmission method. Furthermore, to evaluate the feasibility of the proposed method, we investigated the effectiveness of network delay reduction with existing computational capability and the requirements in the future. As a result, we found that the proposed scheme may mitigate network delay by one to two frames, even with existing computational capability under limited conditions.

Automatic detection of prohibited items is vital in helping security staff be more efficient while improving the public safety index. However, prohibited item detection within X-ray security inspection images is limited by various factors, including the imbalance distribution of categories, diversity of prohibited item scales, and overlap between items. In this paper, we propose to leverage the Poisson blending algorithm with the Canny edge operator to alleviate the imbalance distribution of categories maximally in the X-ray images dataset. Based on this, we improve the cascade network to deal with the other two difficulties. To address the prohibited scale diversity problem, we propose the Re-BiFPN feature fusion method, which includes a coordinate attention atrous spatial pyramid pooling (CA-ASPP) module and a recursive connection. The CA-ASPP module can implicitly extract direction-aware and position-aware information from the feature map. The recursive connection feeds the CA-ASPP module processed multi-scale feature map to the bottom-up backbone layer for further multi-scale feature extraction. In addition, a Rep-CIoU loss function is designed to address the overlapping problem in X-ray images. Extensive experimental results demonstrate that our method can successfully identify ten types of prohibited items, such as Knives, Scissors, Pressure, etc. and achieves 83.4% of mAP, which is 3.8% superior to the original cascade network. Moreover, our method outperforms other mainstream methods by a significant margin.

A 150 GHz fundamental oscillator employing an inter-stage matching network based on a transmission line is presented in this letter. The proposed oscillator consists of a two-stage common-emitter amplifier loop, whose inter-stage connections are optimized to meet the oscillation condition. The oscillator is designed in a 130-nm SiGe BiCMOS process that offers fT and fMAX of 350 GHz and 450 GHz. According to simulation results, an output power of 3.17 dBm is achieved at 147.6 GHz with phase noise of -115 dBc/Hz at 10 MHz offset and figure-of-merit (FoM) of -180 dBc/Hz.

A wireless sensor terminal module of 5cc size (2.5 cm × 2.5 cm × 0.8 cm) that does not require a battery is proposed by integrating three kinds of circuit technologies. (i) a low-power sensor interface: an FM modulation type CMOS sensor interface circuit that can operate with a typical power consumption of 24.5 μW was fabricated by the 0.7-μm CMOS process technology. (ii) power supply to the sensor interface circuit: a wireless power transmission characteristic to a small-sized PCB spiral coil antenna was clarified and applied to the module. (iii) wireless sensing from the module: backscatter communication technology that modulates the signal from the base terminal equipment with sensor information and reflects it, which is used for the low-power sensing operation. The module fabricated includes a rectifier circuit with the PCB spiral coil antenna that receives wireless power transmitted from base terminal equipment by electromagnetic resonance coupling and converts it into DC power and a sensor interface circuit that operates using the power. The interface circuit modulates the received signal with the sensor information and reflects it back to the base terminal. The module could achieve 100 mm communication distance when 0.4 mW power is feeding to the sensor terminal.

L-type LC/CL matching circuits are well known for their simple analytical solutions and have been applied to many radio-frequency (RF) circuits. When actually constructing a circuit, parasitic elements are added to inductors and capacitors. Therefore, each L and C element has a self-resonant frequency, which affects the characteristics of the matching circuit. In this paper, the parallel parasitic capacitance to the inductor and the series parasitic inductor to the capacitance are taken up as parasitic elements, and the details of the effects of the self-resonant frequency of each element on the S11, voltage standing wave ratio (VSWR) and S21 characteristics are reported. When a parasitic element is added, each characteristic basically tends to deteriorate as the self-resonant frequency decreases. However, as an interesting feature, we found that the combination of resonant frequencies determines the VSWR and passband characteristics, regardless of whether it is the inductor or the capacitor.

Wide deployment of artificial intelligence (AI) is inducing exponentially growing energy consumption. Traditional digital platforms are becoming difficult to fulfill such ever-growing demands on energy efficiency as well as computing latency, which necessitates the development of high efficiency analog hardware platforms for AI. Recently, optical and electrooptic hybrid computing is reactivated as a promising analog hardware alternative because it can accelerate the information processing in an energy-efficient way. Integrated photonic circuits offer such an analog hardware solution for implementing photonic AI and machine learning. For this purpose, we proposed a photonic analog of support vector machine and experimentally demonstrated low-latency and low-energy classification computing, which evidences the latency and energy advantages of optical analog computing over traditional digital computing. We also proposed an electrooptic Hopfield network for classifying and recognizing time-series data. This paper will review our work on implementing classification computing and Hopfield network by leveraging silicon photonic circuits.

This article reviews the author’s group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author’s group own experiences are presented as well as their research motivations.

Despite the increasing use of conversational artificial intelligence (AI) in online discussion environments, few studies explore the application of AI as a facilitator in forming problem-solving debates and influencing opinions in cross-venue scenarios, particularly in diverse and war-ravaged countries. This study aims to investigate the impact of AI on enhancing participant engagement and collaborative problem-solving in online-mediated discussion environments, especially in diverse and heterogeneous discussion settings, such as the five cities in Afghanistan. We seek to assess the extent to which AI participation in online conversations succeeds by examining the depth of discussions and participants' contributions, comparing discussions facilitated by AI with those not facilitated by AI across different venues. The results are discussed with respect to forming and changing opinions with and without AI-mediated communication. The findings indicate that the number of opinions generated in AI-facilitated discussions significantly differs from discussions without AI support. Additionally, statistical analyses reveal quantitative disparities in online discourse sentiments when conversational AI is present compared to when it is absent. These findings contribute to a better understanding of the role of AI-mediated discussions and offer several practical and social implications, paving the way for future developments and improvements.

This paper presents the design and implementation of an automated multi-phase facilitation agent based on LLM to realize inclusive facilitation and efficient use of a large language model (LLM) to facilitate realistic discussions. Large-scale discussion support systems have been studied and implemented very widely since they enable a lot of people to discuss remotely and within 24 hours and 7 days. Furthermore, automated facilitation artificial intelligence (AI) agents have been realized since they can efficiently facilitate large-scale discussions. For example, D-Agree is a large-scale discussion support system where an automated facilitation AI agent facilitates discussion among people. Since the current automated facilitation agent was designed following the structure of the issue-based information system (IBIS) and the IBIS-based agent has been proven that it has superior performance. However, there are several problems that need to be addressed with the IBIS-based agent. In this paper, we focus on the following three problems: 1) The IBIS-based agent was designed to only promote other participants' posts by replying to existing posts accordingly, lacking the consideration of different behaviours taken by participants with diverse characteristics, leading to a result that sometimes the discussion is not sufficient. 2) The facilitation messages generated by the IBIS-based agent were not natural enough, leading to consequences that the participants were not sufficiently promoted and the participants did not follow the flow to discuss a topic. 3) Since the IBIS-based agent is not combined with LLM, designing the control of LLM is necessary. Thus, to solve the problems mentioned above, the design of a phase-based facilitation framework is proposed in this paper. Specifically, we propose two significant designs: One is the design for a multi-phase facilitation agent created based on the framework to address problem 1); The other one is the design for the combination with LLM to address problem 2) and 3). Particularly, the language model called “GPT-3.5” is used for the combination by using corresponding APIs from OPENAI. Furthermore, we demonstrate the improvement of our facilitation agent framework by presenting the evaluations and a case study. Besides, we present the difference between our framework and LangChain which has generic features to utilize LLMs.

A method for bandwidth enhancement of radar cross section (RCS) reduction by metasurfaces was studied. Scattering cancellation is one of common methods for reducing RCS of target scatterers. It occurs when the wave scattered by the target scatterer and the wave scattered by the canceling scatterer are the same amplitude and opposite phase. Since bandwidth of scattering cancellation is usually narrow, we proposed the bandwidth enhancement method using metasurfaces, which can control the frequency dependence of the scattering phase. We designed and fabricated a metasurface composed of a patch array on a grounded dielectric substrate. Numerical and experimental evaluations confirmed that the metasurface enhances the bandwidth of 10dB RCS reduction by 52% bandwidth ratio of the metasurface from 34% bandwidth ratio of metallic cancelling scatterers.

Displacement current is the last piece of the puzzle of electromagnetic theory. Its existence implies that electromagnetic disturbance can propagate at the speed of light and finally it led to the discovery of Hertzian waves. On the other hand, since magnetic fields can be calculated only with conduction currents using Biot-Savart's law, a popular belief that displacement current does not produce magnetic fields has started to circulate. But some people think if this is correct, what is the displacement current introduced for. The controversy over the meaning of displacement currents has been going on for more than hundred years. Such confusion is caused by forgetting the fact that in the case of non-stationary currents, neither magnetic fields created by conduction currents nor those created by displacement currents can be defined. It is also forgotten that the effect of displacement current is automatically incorporated in the magnetic field calculated by Biot-Savart's law. In this paper, mainly with the help of Helmholtz decomposition, we would like to clarify the confusion surrounding displacement currents and provide an opportunity to end the long standing controversy.

In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.

In this work, template attacks that aimed to leak the nonce were performed on 256-bit ECDSA hardware to evaluate the resistance against side-channel attacks. The target hardware was an ASIC and was revealed to be vulnerable to the combination of template attacks and lattice attacks. Furthermore, the attack result indicated it was not enough to fix the MSB of the nonce to 1 which is a common countermeasure. Also, the success rate of template attacks was estimated by simulation. This estimation does not require actual hardware and enables us to test the security of the implementation in the design phase. To clarify the acceptable amount of the nonce leakage, the computational cost of lattice attacks was compared to that of ρ method which is a cryptanalysis method. As a result, the success rate of 2-bit leakage of the nonce must be under 62% in the case of 256-bit ECDSA. In other words, SNR must be under 2-4 in our simulation model.

Logic circuits based on a photonic integrated circuit (PIC) have attracted significant interest due to their ultra-high-speed operation. However, they have a fundamental disadvantage that a large amount of the optical signal power is discarded in the path from the optical source to the optical output, which results in significant power consumption. This optical signal power loss is called a garbage output. To address this issue, this paper considers a circuit design without garbage outputs. Although a method for synthesizing an optical logic circuit without garbage outputs is proposed, this synthesis method can not obtain the optimal solution, such as a circuit with the minimum number of gates. This paper proposes a cross-bar gate logic (CBGL) as a new logic structure for optical logic circuits without garbage outputs, moreover enumerates the CBGLs with the minimum number of gates for all three input logic functions by an exhaustive search. Since the search space is vast, our enumeration algorithm incorporates a technique to prune it efficiently. Experimental results for all three-input logic functions demonstrate that the maximum number of gates required to implement the target function is five. In the best case, the number of gates in enumerated CBGLs is one-half compared to the existing method for optical logic circuits without garbage outputs.