The rapid development of a global navigation satellite system (GNSS) has raised the demand for spacecraft navigation, particularly for lunar spacecraft (LS). First, instead of the traditional approach of combining the united X-band system (UXB) with very-long-baseline interferometry (VLBI) by a terrestrial-based observing station in Chinese deep-space exploration, the spacecraft navigation based on inter-satellite link (ISL) is proposed because the spatial coverage of the GNSS downstream signals is too narrow to be used for LS navigation. Second, the feasibility of LS navigation by using ISL wide beam signals has been analyzed with the following receiving parameters: the geometrical dilution of precision (GDOP) and the carrier-to-noise ratio (C/N0) for satellites autonomously navigation of ISL and LS respectively; the weighting distance root-mean-square (wdrms) for the combination of both navigation modes. Third, to be different from all existing spacecraft ISL and GNSS navigation methods, an ISL annular beam transmitting antenna has been simulated to minimize the wdrms (1.138m) to obtain the optimal beam coverage: 16°-47° on elevation angle. Theoretical calculations and simulations have demonstrated that both ISL autonomous navigation and LS navigation can be satisfied at the same time. Furthermore, an onboard annular wide beam ISL antenna with optimized parameters has been designed to provide a larger channel capacity with a simpler structure than that of the existing GPS ISL spot beam antenna, a better anti-jamming performance than that of the former GPS ISL UHF-band wide band antenna, and a wider effectively operating area than the traditional terrestrial-based measurement. Lastly, the possibility and availability of applying an ISL receiver with an annular wide beam antenna on the Chinese Chang'E-5T (CE-5T) reentry experiment for autonomous navigation are analyzed and verified by simulating and comparing the ISL receiver with the practiced GNSS receiver.

Storage-Class Memory (SCM) and NAND flash hybrid Solid-State Drive (SSD) has advantages of high performance and low power consumption compared with NAND flash only SSD. In this paper, first, three SSD configurations are investigated. Three different SCMs are used with 0.1 µs, 1 µs and 10 µs read/write latencies, respectively, and the required SCM/NAND flash capacity ratios are analyzed to maintain the same SSD performance. Next, by using the three SSD configurations, the variation of SSD reliability, performance and cost are analyzed by changing error correction strengths. The SSD reliability of acceptable SCM and NAND flash Bit Error Rates (BERs) is limited by achieving specified SSD performance with error correction, and/or limited by SCM and NAND flash parity size and SSD cost. Lastly, the SSD replacement cost is also analyzed by considering the limitation of NAND flash write/erase cycles. The purpose of this paper is to provide a design guideline for obtaining high performance, highly reliable and cost-effective SCM/NAND hybrid structure SSD with ECC.

Modern web users may encounter a browser security threat called drive-by-download attacks when surfing on the Internet. Drive-by-download attacks make use of exploit codes to take control of user's web browser. Many web users do not take such underlying threats into account while clicking URLs. URL Blacklist is one of the practical approaches to thwarting browser-targeted attacks. However, URL Blacklist cannot cope with previously unseen malicious URLs. Therefore, to make a URL blacklist effective, it is crucial to keep the URLs updated. Given these observations, we propose a framework called automatic blacklist generator (AutoBLG) that automates the collection of new malicious URLs by starting from a given existing URL blacklist. The primary mechanism of AutoBLG is expanding the search space of web pages while reducing the amount of URLs to be analyzed by applying several pre-filters such as similarity search to accelerate the process of generating blacklists. AutoBLG consists of three primary components: URL expansion, URL filtration, and URL verification. Through extensive analysis using a high-performance web client honeypot, we demonstrate that AutoBLG can successfully discover new and previously unknown drive-by-download URLs from the vast web space.

This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm2.

The individual steps of UV imprint lithography have been explained in detail from the points of manufacturing nano-structures. The applications to photonic devices have been also introduced.

Traffic is a key aspect of everyday life. Its study, as it happens with other complex phenomena, has found in simulation a basic tool. However, the use of simulations faces important limitations. Building them requires considering different aspects of traffic (e.g. urbanism, car features, and individual drivers) with their specific theories, that must be integrated to provide a coherent model. There is also a variety of simulation platforms with different requirements. Many of these problems demand multi-disciplinary teams, where the different backgrounds can hinder the communication and validation of simulations. The Model-Driven Engineering (MDE) of simulations has been proposed in other fields to address these issues. Such approaches develop graphical Modelling Languages (MLs) that researchers use to model their problems, and then semi-automatically generate simulations from those models. Working in this way promotes communication, platform independence, incremental development, and reutilisation. This paper presents the first steps for a MDE framework for traffic simulations. It introduces a tailored extensible ML for domain experts. The ML is focused on human actions, so it adopts an Agent-Based Modelling perspective. Regarding traffic aspects, it includes concepts commonly found in related literature following the Driver-Vehicle-Environment model. The language is also suitable to accommodate additional theories using its extension mechanisms. The approach is supported by an infrastructure developed using Eclipse MDE projects: the ML is specified with Ecore, and a model editor and a code generator tools are provided. A case study illustrates how to develop a simulation based on a driver's behaviour theory for a specific target platform using these elements.

In this paper, we present a modified image rejection method that uses imbalance compensation techniques for phase and gain in low-intermediate frequency (IF) software-defined radio (SDR) receivers. In low-IF receivers, the image frequency signal interferes with the desired signal owing to the phase and gain imbalances caused by analog devices. Thus, it is difficult to achieve the required image rejection ratio (IRR) of over 60dB without compensation. To solve this problem, we present modified blind compensation techniques based on digital signal processing using a feedback control loop with a practical computation process. The modified method can reduce the complexity when a hardware logic circuit is used, like an FPGA. The simulation and experimental results verify that the modified method achieves an IRR greater than 50-60dB for both the carrier and the modulated waves.

In PQCrypto 2013, Yasuda, Takagi and Sakurai proposed a new signature scheme as one of multivariate public key cryptosystems (MPKCs). This scheme (called YTS) is based on the fact that there are two isometry classes of non-degenerate quadratic forms on a vector space with a prescribed dimension. The advantage of YTS is its efficiency. In fact, its signature generation is eight or nine times faster than Rainbow of similar size. For the security, it is known that the direct attack, the IP attack and the min-rank attack are applicable on YTS, and the running times are exponential time for the first and the second attacks and sub-exponential time for the third attack. In the present paper, we give a new attack on YTS whose approach is to use the diagonalization of matrices. Our attack works in polynomial time and it actually recovers equivalent secret keys of YTS having 140-bits security against min-rank attack in around fifteen seconds.

This study explored the question of how to minimize older drivers' accidents and to identify at-risk drivers by analyzing their driving performance. Previous traffic research reported that there were two factors involved in risky driving, namely driving risk perception and risky driving attitude. We investigated these two factors as indicators of an at-risk driver by using large-scale test data from license renewal tests that are obligatory for Japanese drivers who are 70 years of age or older. The tests include a driving simulator test, an on-road test, and a cognitive screening test. By using these assessments and predictions made with renewal driving tests, we were able to indicate the possibility of identifying at-risk drivers.

The controllability of complex networks has attracted increasing attention within various scientific fields. Many power grids are complex networks with some common topological characteristics such as small-world and scale-free features. This Letter investigate the controllability of some real power grids in comparison with classical complex network models with the same number of nodes. Several conclusions are drawn after detailed analyses using several real power grids together with Erdös-Rényi (ER) random networks, Wattz-Strogatz (WS) small-world networks, Barabási-Albert (BA) scale-free networks and configuration model (CM) networks. The main conclusion is that most driver nodes of power grids are hub-free nodes with low nodal degree values of 1 or 2. The controllability of power grids is determined by degree distribution and heterogeneity, and power grids are harder to control than WS networks and CM networks while easier than BA networks. Some power grids are relatively difficult to control because they require a far higher ratio of driver nodes than ER networks, while other power grids are easier to control for they require a driver node ratio less than or equal to ER random networks.

An earthquake is a destructive natural disaster, which cannot be predicted accurately and causes devastating damage and losses. In fact, many of the damages can be prevented if people know what to do during and after earthquakes. Earthquake education is the most important method to raise public awareness and mitigate the damage caused by earthquakes. Generally, earthquake education consists of conducting traditional earthquake drills in schools or communities and experiencing an earthquake through the use of an earthquake simulator. However, these approaches are unrealistic or expensive to apply, especially in underdeveloped areas where earthquakes occur frequently. In this paper, an earthquake drill simulation system based on virtual reality (VR) technology is proposed. A User is immersed in a 3D virtual earthquake environment through a head mounted display and is able to control the avatar in a virtual scene via Kinect to respond to the simulated earthquake environment generated by SIGVerse, a simulation platform. It is a cost effective solution and is easy to deploy. The design and implementation of this VR system is proposed and a dormitory earthquake simulation is conducted. Results show that powerful earthquakes can be simulated successfully and the VR technology can be applied in the earthquake drills.

Address configuration is a key problem in data center networks. The core issue of automatic address configuration is assigning logical addresses to the physical network according to a blueprint, namely logical-to-device ID mapping, which can be formulated as a graph isomorphic problem and is hard. Recently years, some work has been proposed for this problem, such as DAC and ETAC. DAC adopts a sub-graph isomorphic algorithm. By leveraging the structure characteristic of data center network, DAC can finish the mapping process quickly when there is no malfunction. However, in the presence of any malfunctions, DAC need human effort to correct these malfunctions and thus is time-consuming. ETAC improves on DAC and can finish mapping even in the presence of malfunctions. However, ETAC also suffers from some robustness and efficiency problems. In this paper, we present GA-MAP, a data center networks address mapping algorithm based on genetic algorithm. By intelligently leveraging the structure characteristic of data center networks and the global search characteristic of genetic algorithm, GA-MAP can solve the address mapping problem quickly. Moreover, GA-MAP can even finish address mapping when physical network involved in malfunctions, making it more robust than ETAC. We evaluate GA-MAP via extensive simulation in several of aspects, including computation time, error-tolerance, convergence characteristic and the influence of population size. The simulation results demonstrate that GA-MAP is effective for data center addresses mapping.

Cassuto and Blaum proposed new error correcting codes which are called symbol-pair codes. They presented a coding framework for channels whose outputs are overlapping pairs of symbols in storage applications. Such channels are called symbol-pair read channels. The pair distance and pair error are used in symbol-pair read channels. Cassuto et al. and Yaakobi et al. presented decoding algorithms for symbol-pair codes. However, their decoding algorithms cannot always correct errors whose number is not more than half the minimum pair distance. In this paper, we propose a new decoding algorithm using syndromes of symbol-pair codes. In addition, we show that the proposed algorithm can correct all pair errors within the pair error correcting capability.

A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

The researches on model-based testing mainly focus on the models with single component, such as FSM and EFSM. For the network protocols which have multiple components communicating with messages, CFSM is a widely accepted solution. But in some network protocols, parallel and data-shared components maybe exist in the same network entity. It is infeasible to precisely specify such protocol by existing models. In this paper we present a new model, Parallel Parameterized Extended Finite State Machine (PaP-EFSM). A protocol system can be modeled with a group of PaP-EFSMs. The PaP-EFSMs work in parallel and they can read external variables form each other. We present a 2-stage test generation approach for our new models. Firstly, we generate test sequences for internal variables of each machine. They may be non-executable due to external variables. Secondly, we process the external variables. We make the sequences for internal variables executable and generate more test sequences for external variables. For validation, we apply this method to the conformance testing of real-life protocols. The devices from different vendors are tested and implementation faults are exposed.

A field multiplication in the extended binary field is often expressed using Toeplitz matrix-vector products (TMVPs), whose matrices have special properties such as symmetric or triangular. We show that such TMVPs can be efficiently implemented by taking advantage of some properties of matrices. This yields an efficient multiplier when a field multiplication involves such TMVPs. For example, we propose an efficient multiplier based on the Dickson basis which requires the reduced number of XOR gates by an average of 34% compared with previously known results.

A low-complexity time-frequency multiplex estimator and low-complexity equalizer transceiver design are proposed to combat the problems of RF impairment associated with zero-IF transceiver of multi-carrier systems. Moreover, the proposed preambles can estimate the transmitter (TX) in-phase and quadrature-phase (IQ) imbalance, carrier frequency offset (CFO), and channel impulse response parameters. The proposed system has two parts. First, all parameters of the impairments are estimated by the designed time-frequency multiplex estimator. Second, the estimated parameters are used to compensate the above problems and detect the transmitted signal with low complexity. Simulation results confirm that the proposed estimator performs reliably with respect to IQ imbalance, CFO, and multipath fading channel effects.

This paper proposes the MIMO MC-CDMA channel estimation method for the various mobile environments. The distinctive feature of the proposed method is possible to robustly estimate with respect to the mobile velocity using the Kalman filter with the colored driving source. Effectiveness of the proposed method are shown by computer simulations.

Viterbi decoding is commonly used for several protocols, but computational cost is quite high and thus it is necessary to implement it effectively. This paper describes GPU implementation of Viterbi decoder utilizing three-point Viterbi decoding algorithm (TVDA), in which the received bits are divided into multiple chunks and several chunks are decoded simultaneously. Coalesced access and Warp Shuffle, which is new instruction introduced are also utilized in order to improve decoder performance. In addition, iterative execution of parallel chunks decoding reduces the latency of proposed Viterbi decoder in order to utilize the decoder as a part of GPU-based SDR transceiver. As the result, the throughput of proposed Viterbi decoder is improved by 23.1%.

In this paper, a new single soft switched forward converter with a self driven synchronous rectification (SDSR) is introduced. In the proposed converter, a soft switching condition (ZCS turn on and ZVS turn off) is provided for the switch, by an auxiliary circuit without any extra switch. In additional, this auxiliary circuit does not impose high voltage or current stresses on the converter. Since the proposed converter uses SDSR to reduce conductive loss of output rectifier, the rectifier switches are switched under soft switching condition. So, the conductive and switching losses on the converter reduce considerably. Also, implementing control circuit of this converter is very simple, due to the self-driven method employed in driving synchronous rectification and the converter is controlled by pulse width modulation (PWM). The experimental results of the proposed converter are presented to confirm the theoretical analysis.