Intricate Speech Communication Mode (I-SC Mode) is observed in verbal interaction during ISDN-TV conferencing. It is characterized by conflicts and multiple interactions of speech. I-SC Mode might cause mental stress to participants and be obstacles for smooth communication. However, the reasons of I-SC Mode on the environment of information transmission are hitherto unknown. Furthermore, analyses on the talks inside a conference site (LT: local talk or a talk inside a local site) and between remote sites (MT: media talk or a talk between remote sites) are originally conceived on assumed differences in cognitive distance and media intimacy. This study deals with communication effects/barriers and cognitive distance/intimacy of media correlated with audio-video transmission signals and speech modes or talk types and response delay in human speech interactions by using an innovated conference model (decision-making transaction model: DT-Model) in synchronous ISDN-TV conference systems (SYN) and asynchronous ones (ASYN). The effects of intricate communication can be predicted to a certain extent and in some ways. In I-SC Mode, because a timely answer can not be received from recipients (or partner), response time delay and response rate are analyzed. These factors are thus analyzed with an innovated dynamic model, where the recognizable acceptance of delay is evaluated. The nonlinear model shows that the larger the response time delay, the lower the response rate becomes. Comparing the response rate between SYN and ASYN, the latter is notably lower than the former. This indicates that the communication efficiency is lower in ASYN. An I-SC Mode is the main mode that occurs during ASYN conferences, and this in turn causes psychological stress. Statistics show the prevalence of a high incidence of complicated plural talks and a low response rate exists as the main factors preventing smooth human-to-human communication. Furthermore, comparing the response delays in face-to-face LT (Tf) and machine-mediated MT (Tm), human communication delay is significantly extended by the effects of initial mechanical delays. Therefore, cognitive intimacy of media is clearly affected by the existence of physical distance.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

Asynchronous Transfer Mode (ATM) is a promised bearer transmission service for high speed multimedia LAN. Recently, high speed multimedia ATM LAN products have been available. Therefore, in order to interconnect them, the multimedia backbone LAN, which has the expandable high throughput over 10Gbps, supporting multicast, multi-QoS, and many interfaces including 622 Mbps, will be widely required. In this paper, the VLSI oriented input and output buffered switch architecture is proposed as the hardware architecture for multimedia backbone switch node. This paper describes that the chip set consisting of four VLSIs, that is, the switch element, the switch access, the distributor/arbiter, and the multiplexer/demultiplexer, can realize the backbone switch core, and the main specifications required to each VLSI are derived.

This paper describes the results of tests that measured the allowable delay between images and tactile information via a force feedback device. In order to investigate the allowable delay, two experiments were performed: 1) subjective evaluation in real space and 2) subjective evaluation in virtual space using a force feedback device.

For a fuzzy control of manipulated variable so as to match a required output of a plant, tuning of fuzzy rules are necessary. For its purpose, various methods to tune their rules automatically have been proposed. In these method, some of them necessitate much time for its tuning, and the others are lacking in the generalization capability. In the fuzzy control by the steepest descent method, a use of piecewise linear membership functions (MSFs) has been proposed. In this algorithm, MSFs of the premise for each fuzzy rule are tuned having no relation to the other rules. Besides, only the MSFs corresponding to the given input and output data for the learning can be tuned efficiently. Comparing with the conventional triangular form and the Gaussian distribution of MSFs, an expansion of the expressiveness is indicated. As a result, for constructing the inference rules, the training cycles can be reduced in number and the generalization capability to express the behavior of a plant is expansible. An effectiveness of this algorithm is illustrated with an example of a parallel parking of an autonomous mobile robot.

When circuits which include inductive loads are turned off by contact, showering noise generates across contact gap. Showering noise waveforms seem not to be stable in the case that wire-spring relay contact is used to turn on/off inductive load. It seems that various factors are concerned in the irregularity of showering noise waveforms. This paper clarifies the relation between showering noise waveform and the cathodic contact surface variation with the number of contact operation, and moving velocity of contact.

A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

This paper discusses the problems of largest similar substructures (in short, LSS) in rooted and unordered trees (in short, R-trees) and those in unrooted and unordered trees (in short, trees). For two R-trees (or trees) Ta and Tb, LSS in Tb to Ta is defined, and two algorithms for finding one of the LSSs for R-trees and that for trees are proposed. The time and space complexities of both algorithms are OT (m3NaNb) and OS(mNaNb), respectively, where m is the largest degree of a vertex of Ta and Tb, and Na(Nb)is the number of vertices of Ta(Tb).

Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

This paper proposes a mutual exclusion method that is unified for the parallel and distributed systems. The method partially serializes requests into partial queues of requests, which are next totally serialized into a main queue. A request in the main queue is authorized to enter the critical section (CS) when the request receives the privilege token from the previous request in the queue. In the distributed system of N sites that each is a parallel system, mutual exclusion is performed by cooperation of two algorithms based on the same method. The algorithm for the distributed system works on a logical network (that is a directed tree) of S ( N) sites. The algorithm for each site produces a local-main queue of requests. The chunk of requests in the local queue is concatenated at a time to the partial queue of the distributed system. The the cost of mutual exclusion -- the number of intersite messages required per CS entry -- is reduced to O(1) (between 0 and 3).

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

For the purpose of automatic speech recognition, language models (LMs) are used to predict possible succeeding words for a given partial word sequence and thereby to reduce the search space. In this paper several kinds of stochastic language models (SLMs) are evaluated-bigram, trigram, hidden Markov model (HMM), bigram-HMM, stochastic context-free grammar (SCFG) and hand-written Bunsetsu Grammar. To compare the predictive power of these SLMs, the evaluation was conducted from two points of views: (1) relationship between the number of model parameters and entropy, (2) predictive rate of succeeding part of speech (POS) and succeeding word. We propose a new type of bigram-HMM and compare it with the other models. Two kinds of approximations are tried and examined through experiments. Results based on both of English Brown-Corpus and Japanese ATR dialog database showed that the extended bigram-HMM had better performance than the others and was more suitable to be a language model.

A tree embedded in a plane can be characterized as an unrooted and cyclically ordered tree (CO-tree). This paper describes new definitions of three distances between CO-trees and their computing methods. The proposed distances are based on the Tai Mapping, the structure preserving mapping and the strongly structure preserving mapping, respectively, and are called the Tai distance (TD), the structure preserving distance (SPD) and the strongly structure preserving distance (SSPD), respectively. The definitions of distances and their computing methods are simpler than those of the old definitions and computing methods, respectively. TD and SPD by the new definitions are more sensitive than those by the old ones, and SSPDs by both definitions are equivalent. The time complexities of computing TD, SPD and SSPD between CO-trees Ta and Tb are OT (N2aN2a), OT(maNaN2b) and OT(mambNaNb), respectively, where Na(Nb) and ma(mb) are the number of vertices in tree Ta(Tb)and the maximum degree of a vertex in Ta(Tb), respectively. The space complexities of these methods are OS(NaNb).

In this paper cosets of the second order Reed-Muller code of length 2m, denoted RMm,2, in the third order Reed-Muller code of the same length, denoted RMm,3, are studied. The set of cosets, RMm,3/RMm,2 is partitioned into blocks. Two cosets are in the same block, if and only if there is a transformation in the general linear group by which one coset is transformed into the other. Two cosets in the same block have the same weight distribution. For the code length less than or equal to 128, the representative coset leader of each block is presented and the weight distribution of cosets in the block is computed. By using these results, the extended code of a cyclic code of length 128 between RM7,2 and RM7,3 can be decomposed into a set of cosets in RM7,3/RM7,2, and its weight distribution can be derived. Several cyclic codes to length 127 are shown to be equivalent and some new linear unequal error protection codes are found.

Protective layers in AC plasma display panels (PDP) are usually formed by vacuum vapor deposition or sputtering. It is important to study the protective MgO layer by means of screen-printing for fabricating a large size PDP and reducing its cost. With the objectives of enlarging the panel size and reducing cost, we studied the fabrication of the protective MgO layer by means of screen-printing. In this study, we succeeded in lowering the drive voltage by using a MgO powder prepared by vapor phase oxidation instead of conventional decomposition of the magnesium salt. Further, by adding a MgO liquid binder, we attained a good luminous efficiency twice as high as that attained with a sputtered protective layer and lowered the drive voltage. When this protective layer was combined with He-Xe gas enclosure, the half-life of luminance was 5,000 hours. With Ne-Xe gas, the luminance deteriorated no more than 40% after 5,000 hours. A screen-printed protective MgO layer containing no MgO liquid binder showed a short half-life of 800 hours even with the use of Ne-Xe gas. In this case, the discharge voltage changed greatly and some cells did not discharge. It is concluded that the combination of an ultrafine MgO powder prepared by vapor phase oxidation and a MgO liquid binder can clear the way for making AC PDPs with a long lifetime, high efficiency, and low voltage a practical reality.

We propose a parallel parsing algorithm based on Earley's method, which works in O(log2n) time using O(n4.752) processors on CREW PRAM. This algorithm runs with less number of precessors compared with previously proposed W. Rytter's algorithm.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

To realize high-speed computations in a residue number system (RNS), an implementation method for residue arithmetic circuits using signed-digit (SD) number representation is proposed. Integers mp = (2p-1) known as Mersenne numbers are used as moduli, so that modulo mp addition can be performed by an end-around-carry SD adder and the addition time is independent of the word length of operands. Using a binary modulo mp SD adder tree, the modulo mp multiplication can be performed in a time proportional to log2p.

We have developed a complete chromium oxide (Cr2O3) passivated gas tubing system by introducing ferritic stainless steel instead of conventional austenitic stainless steel (SUS316L). 100% Cr2O3 passivation film can be formed on electropolished ferritic stainless steel surface because the diffusion coefficient of Cr in ferritic stainless steel is 104 times larger than in austenitic stainless steel. In ferritic stainless steel, moreover, welded bead surface is covered by 100% Cr2O3 pas-sivated film by an introduction of advanced welding technology.