The paper discusses properties of YBaCuO thick films produced by screen printing method and followed sintering of a paste made from pre-annealed powder on Yttrium Stabilized Zirconia (YSZ) and MgO substrates. The prepared films have been studied by X-ray diffraction, scanning electron microscopy (SEM) and resistance vs. temperature measurements.

This paper presents the M-LCELP (Multi-mode Learned Code Excited LPC) speech coder, which has been developed for the next generation half-rate digital cellular telephone systems. M-LCELP develops the following techniques to achieve high-quality synthetic speech at 4kb/s with practically reasonable computation and memory requirements: (1) Multi-mode and multi-codebook coding to improve coding efficiency, (2) Pitch lag differential coding with pitch tracking to reduce lag transmission rate, (3) A two-stage joint design regular-pulse codebook with common phase structure in voiced frames, to drastically reduce computation and memory requirements, (4) An efficient vector quantization for LSP parameters, (5) An adaptive MA type comb filter to suppress excitation signal inter-harmonic noise. The MOS subjective test results demonstrate that 4.075kb/s M-LCELP synthetic speech quality is mostly equivalent to that for a North American full-rate standard VSELP coder. M-LCELP codec requires 18 MOPS computation amount. The codec has been implemented using 2 floating-point dsp chips.

Three-dimensional display technologies that require special glasses are not suitable for telecommunications because wearing glasses is inconvenient and it is defficult to observe facial expressions. Our previous 6.3-inch 3D display was inadequate for presenting images with realistic sensation. In this paper, a direct view 15-inch 3D display is described. The display is made up of a l5-inch TFT LCD and a composite lenticular sheet (LS), and uses the head tracking technique. Quantitative evaluation of the stereoscopic sensation of the display was studied using the 3D display, and better stereoscopic sensation values were obtained compared with a 2D display mode, thus comfirming the display's usefulness.

This paper presents a new approach to the recovery of 3-D structure from multiple pairs of images from different viewpoints. Searching for the corresponding points between images, which is common in stereopsis, is avoided. Extracted edges from input images are projected back into 3-D space, and their intersections are calculated directly. Many false intersections may appear, but if we have many pair images, true intersections are extracted by appropriate thresholding. Octree representation of the intersections enables this approach. We consider a way to treat adjacent edge piexels as a line segment rather than as individual points, which differs from previous works and leads to a new algorithm. Experimental results using both synthetic and actual images are also described.

In this paper, we analyze high-Tc superconducting (HTS) microstrip antenna (MSA) using modified spectral domain moment method. Although it is assumed that the patch and the ground plane of the MSA are perfect electric conductors (PECs) in the conventional spectral domain method, we modify this method to compute the conduction loss of the HTS-MSA. In our analysis, the effect of the HTS film is introduced by the surface impedance which we can estimate by using the three fluid model and experimental results. This paper presents numerical results about the HTS-MSA, for example, the relations between the thickness of the substrate and the radiation efficiency, the temperature and the resonant frequency, and so forth. And we discuss the effective power range where the performance of the HTS-MSA is superior to that of the Cu-MSA.

A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

This paper presents the history of Flash memories and the basic concept of their functions and also reviews a variety of Flash EEPROM's so far. As Flash memories have two influential features, non-volatility and low cost per bit, they are expected to become a driving force after DRAM's to support the semiconductor industry for the next thirty years, replacing hard and floppy disks which have a large market.

This paper reports on the properties of thin-film thermal switches that are monolithically fabricated on high-Tc superconductive filter. Operating at a wide temperature range of 50-77 K, it was found that the switch could control the center frequency by -10 MHz with an increased insertion loss of less than 0.7 dB. In an on-off switching operation of filter characteristics using thin-film switches, power consumption was approximately 20 mW at 77 K, and the signal decay time as a switching speed was 30 ms at 76 K with a switch current of 70 mA. The decay time decreased exponentially as the switch current or the temperature setting increased.

The data retention characteristics of a Flash memory cell with a self-aligned double poly-Si stacked structure have been drastically improved by applying a bi-polarity write and erase technology which uses uniform Fowler-Nordheim tunneling over the whole channel area both during write and erase. It is clarified experimentally that the detrapping of electrons from the gate oxide to the substrate results in an extended retention time. A bi-polarity write and erase technology also guarantees a wide cell threshold voltage window even after 106 write/erase cycles. This technology results in a highly reliable EEPROM with an extended data retention time.

The magnitude of low frequency noise is studied in a Nb-(nanoconstrictions)-NbN system with adjustable current-voltage characteristics. We find that the magnitude of low frequency noise decreases sharply with increasing the subgap conductivity of the device. We suggest a qualitative explanation of this observation in terms of gradual build up of the nanoconstriction region by field assisted growth. The decrease of low frequency noise is related to the "cleanliness" of the system as measured by the amount of Andreev reflection-related conductivity. The scaling of the magnitude of low frequency noise with device resistance is also discussed.

The issue about document structure recognition and document understanding is today one of interesting subjects from a viewpoint of practical applications. The research objective is to extract the meaningful data from document images interpretatively and also classify them as the predefined item data automatically. In comparison with the traditional image-processing-based approaches, the knowledge-based approaches, which make use of various knowledge in order to interpret structural/constructive features of documents, have been currently investigated as more flexible and applicable methods. In this paper, we propose a totally integrated paradigm for understanding table-form documents from a viewpoint of the architectural framework.

In robot vision system, enormously large computation power is required to perform three-dimensional (3-D) instrumentation and object recognition. However, many kinds of complex and irregular operations are required to make accurate 3-D instrumentation and object recognition in the conventional method for software implementation. In this paper, a VLSI-oriented Model-Based Robot Vision (MBRV) processor is proposed for high-speed and accurate 3-D instrumentation and object recognition. An input image is compared with two-dimensional (2-D) silhouette images which are generated from the 3-D object models by means of perspective projection. Because the MBRV algorithm always gives the candidates for the accurate 3-D instrumentation and object recognition result with simple and regular procedures, it is suitable for the implementation of the VLSI processor. Highly parallel architecture is employed in the VLSI processor to reduce the latency between the image acquisition and the output generation of the 3-D instrumentation and object recognition results. As a result, 3-D instrumentation and object recognition can be performed 10000 times faster than a 28.5 MIPS workstation.

The ultimate minimum energy of switching mechanism for MOS integrated circuits have been studied. This report elucidates the evaluation methods for minimum switching energy of instantaneous discharged mechanism after charging one, namely, recycled energy of the MOS device. Two approaches are implemented to capture this concept. One is a switching energy by the time-dependent gate capacitance (TDGC) model ; the other one by results developed by transient device simulation, which was implemented using Finite Element Method (FEM). It is understood that the non-recycled minimum swhiching energies by both approaches show a good agreement. The recycled energies are then calculated at various sub-micron gate MOS/SOI devices and can be ultra-low power of the MOS integrated circuits, which may be possible to build recycled power circuitry for super energy-saving in the future new MOS LSI. From those results, (1) the TDGC is simultaneously verified by consistent match of the non-recycled minimum switching energies; (2) the recycled switching energy is found to be the ultimate lower bound of power for MOS device; (3) the recycled switching energy can be saved up to around 80% of that of current MOS LSI.

Pitch frequency is a basic characteristic of human voice, and pitch extraction is one of the most important studies for speech recognition. This paper describes a simple but effective technique to obtain correct pitch frequency from candidates (pitch candidates) extracted by the short-range autocorrelation function. The correction is performed by a neural network in consideration of the time coutinuation that is realized by referring to pitch candidates at previous frames. Since the neural network is trained by the back-propagation algorithm with training data, it adapts to any speaker and obtains good correction without sensitive adjustment and tuning. The pitch extraction was performed for 3 male and 3 female announcers, and the proposed method improves the percentage of correct pitch from 58.65% to 89.19%.

C-V and I-V characteristics of an n-MOSFET with Si-implanted gate-SiO2 of 50 nm are analyzed by using a test device with large equal channel width and length of 100 µm, and discussed for realizing a large hysteresis window of threshold voltage. Interface trap densities change logarithmically from 31010 to 11012cm2eV1 as the Si-dose at 25 keV increases from zero to 31016cm2. Threshold-voltage changes caused by 25 keV implantaions are as high as 0.2 V. Effective mobilities (subthreshold swings) change from 600 (0.10) to 100 cm2/Vs (0.26 V/decade) as the Si-dose increases from 0 to 31016 cm2 at 25 keV, and both parameters are related with the change of interface trap densities. There is a close relationship between the hysteresis windows of gate current and threshold voltage, and the largest threshold voltage window in a low gate voltage region is obtained for the MOSFET with Si-implantation at 25 keV/31016 cm2.

The studies on the biological effects of ELF electric fields conducted in Japan are reviewed. Among international studies, they are characterized as the studies from the viewpoint of bioengineering. In early studies, the safety standard of high voltage transmission lines was determined by a distinct biological effect, i.e., the sensation of the spark discharge caused by electrostatic induction. In numerical analysis, the field coupling to both animal and human bodies became well understood. Some new measurement techniques were developed which enabled us to evaluate the field exposure on a human body. A system was developed to realize the chronic exposure of an electric field on mice and cats. An optical telemetry technique was developed to measure the physiological response of an animal when it was exposed to an electric field. An ion-current shuttle box was developed to investigate the behavioral change of a rat when it was exposed to an ion-current as well as an electric field. In animal experiments, a mechanism of sensing the field was investigated. The cause of the seasonal change of field sensitivity was found. In cases of chronic exposure, suppression of growth was suspected. In shuttle box studies, an avoidance behavior from an ion-current was quantified. To find whether there are any adverse or beneficial effects of the field exposure on human beings, further study is required to clarify the mechanisms of the biological effects.

In an earlier paper, we have shown that each section of the L-section minimal trellis diagram for a linear block code consists of parallel and structurally identical (except branch labels) subgraphs without cross connections. These parallel subgraphs are called parallel components of the section. In this paper, it is shown that if the sets of path label sequences of two parallel components have a common sequence, then the parallel components have the same branch labels, and the number of parallel components with the same branch labels in each section and the detail structure of each parallel component up to its branch labels are analyzed and expressed in terms of the dimensions of specific linear codes related to the given code. As an example, the 2i-section minimal trellis diagram for a Reed-Muller code is analyzed. Complexity measures of soft-decision maximum likelihood decoding for binary linear block codes are also discussed.

In this paper, a new structure which is useful for the detection of multiple sinusoids is presented. The proposed structure is based on the direct form second-order IIR notch filter using simplified adaptive algorithm. It has been shown that the convergence characteristics of the proposed structure are much improved compared with the previously proposed structure. A cascaded adaptive notch filter using the proposed second-order section is also shown. It takes multiple sinusoids corrupted by white Gaussian noise and produces the individual sinusoids at each of the outputs. The results of computer simulation are shown which confirm the theoretical prediction.