The resistor variation can severely affect current reference sources, which may vary up to ±40% in scaled CMOS processes. In addition, such variations make the opamp design challenging and increase the design margin, impacting power consumption. This paper proposes a Time-Based Current Source (TBCS): a robust and process-scalable reference current source suitable for switched-capacitor (SC) circuits. We construct a delay-locked-loop (DLL) to lock the current-starved inverter with the reference clock, enabling the use of the settled current directly as a reference current. Since the load capacitors determine the delay, the generated current is decoupled from resistor values and enables a robust reference current source. The prototype TBCS fabricated in 28nm CMOS achieved a minimal area of 1200um2. The current variation is suppressed to half compared to BGR based current sources, confirmed in extensive PVT variation simulations. Moreover, when used as the opamp's bias, TBCS achieves comparable opamp GBW to an ideal current source.

In this paper, an algorithm based on Taylor series expansion is proposed to calculate the logarithm (log2x) of IEEE754 binary32 accuracy floating-point number by a multi-domain partitioning method. The general mantissa (1≤x<2) is multiplied by 2, 4, 8, … (or equivalently left-shifted by 1, 2, 3, … bits), the regions of (2≤x<4), (4≤x<8), (8≤x<16),… are considered, and Taylor-series expansion is applied. In those regions, the slope of f(x)=log2 x with respect to x is gentle compared to the region of (1≤x<2), which reduces the required number of terms. We also consider the trade-offs among the numbers of additions, subtractions, and multiplications and Look-Up Table (LUT) size in hardware to select the best algorithm for the engineer's design and build the best hardware device.

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert malicious circuits, called hardware Trojans, into their products, developing an effective hardware-Trojan detection method is strongly required. In this paper, we propose 25 hardware-Trojan features focusing on the structure of trigger circuits for machine-learning-based hardware-Trojan detection. Combining the proposed features into 11 existing hardware-Trojan features, we totally utilize 36 hardware-Trojan features for classification. Then we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on a random-forest classifier. The experimental results demonstrate that the average true positive rate (TPR) becomes 64.2% and the average true negative rate (TNR) becomes 100.0%. They improve the average TPR by 14.8 points while keeping the average TNR compared to existing state-of-the-art methods. In particular, the proposed method successfully finds out Trojan nets in several benchmark circuits, which are not found by the existing method.

Low-hit-zone frequency-hopping sequences (LHZ-FHSs) are frequency-hopping sequences with low Hamming correlation in a low-hit-zone (LHZ), which have important applications in quasi-synchronous communication systems. However, the strict quasi-synchronization may be hard to maintain at all times in practical FHMA networks, it is also necessary to minimize the Hamming correlation for time-shifts outside of the LHZ. The main objective of this letter is to propose a lower bound on the maximum correlation magnitude outside the low-hit-zone for LHZ-FHS sets. It turns out that the proposed bound is tight or almost tight in the sense that it can be achieved by some LHZ-FHS sets.

The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.

Intelligent transportation systems (ITSs) have been extensively studied in recent years to improve the safety and efficiency of transportation. The use of a radar system to enable the ITSs monitor the environment is robust to weather conditions and is less invasive to user privacy. Moreover, equipping the roadside units (RSUs) with radar modules has been deemed an economical and efficient option for ITS operators. However, because the detection and tracking parameters can significantly influence the radar system performance and the best parameters for different scenarios are different, the selection of appropriate parameters for the radar systems is critical. In this study, we investigated radar parameter selection and consequently proposes a parameter selection approach capable of automatically choosing the appropriate detection and tracking parameters for radar systems. The experimental results indicate that the proposed method realizes appropriate selection of parameters, thereby significantly improving the detection and tracking performance of radar systems.

Manufacturers are coping with increasing pressures in quality, cost and efficiency as more and more industries are moving from traditional setup to industry 4.0 based digitally transformed setup due to its numerous playbacks. Within the manufacturing domain organizational structures and processes are complex, therefore adopting industry 4.0 and finding an optimized re-engineered business process is difficult without using a systematic methodology. Authors have developed Business Process Re-engineering (BPR) and Business Process Optimization (BPO) methods but no consolidated methodology have been seen in the literature that is based on industry 4.0 and incorporates both the BPR and BPO. We have presented a consolidated and systematic re-engineering and optimization framework for a manufacturing industry setup. The proposed framework performs Evolutionary Multi-Objective Combinatorial Optimization using Multi-Objective Genetic Algorithm (MOGA). An example process from an aircraft manufacturing factory has been optimized and re-engineered with available set of technologies from industry 4.0 based on the criteria of lower cost, reduced processing time and reduced error rate. At the end to validate the proposed framework Business Process Model and Notation (BPMN) is used for simulations and perform comparison between AS-IS and TO-BE processes as it is widely used standard for business process specification. The proposed framework will be used in converting an industry from traditional setup to industry 4.0 resulting in cost reduction, increased performance and quality.

This letter presents a new framework for synchronous remote online exams. This framework proposes new monitoring of notebooks in remote locations and limited messaging only enabled between students and their instructor during online exams. This framework was evaluated by students as highly effective in minimizing cheating during online exams.

The NIST post-quantum project intends to standardize cryptographic systems that are secure against attacks by both quantum and classical computers. One of these cryptographic systems is NewHope that is a RING-LWE based key exchange scheme. The NewHope Key Encapsulation Method (KEM) allows to establish an encapsulated (secret) key shared by two participants. This scheme defines a private key that is used to encipher a random shared secret and the private key enables the deciphering. This paper presents Fault Information Leakage attacks, using conventional personal computers, if the attacked participant, say Bob, reuses his public key. This assumption is not so strong since reusing the pair (secret, public) keys saves Bob's device computing cost when the public global parameter is not changed. With our result we can conclude that, to prevent leakage, Bob should not reuse his NewHope secret and public keys because Bob's secret key can be retrieved with only 2 communications. We also found that Bob's secret keys can be retrieved for NewHopeToy2, NewHopeToy1 and NewHopeLudicrous with 1, 2, and 3 communications, respectively.

Numerous variable tap-length algorithms can be found in some literature and few strategies are derived from a basic theoretical formula. Thus, some algorithms lack of theoretical depth and their performance are unstable. In view of this point, the novel variable tap-length algorithm which is based on the mixed error cost function is presented in this letter. By analyzing the mixed expectation of the prior and the posterior error, the novel variable tap-length strategy is derived. The proposed algorithm has a more valid proximity to the optimal tap-length and a good convergence ability by the performance analysis. It can solve many deficiencies comprising large fluctuations of the tap-length, the high complexity and the weak steady-state ability. Simulation results demonstrate that the proposed algorithm equips good performance.

Rain attenuation characteristics due to typhoon passage are discussed using the Ku-band BS satellite signal observations conducted by Osaka Electro-Communication University in Neayagawa from 1988 to 2019. The degree of hourly rain attenuation due to rainfall rate is largely enhanced as typhoon passes the east side of the station, while it becomes smaller in the case of west side passage. Compared to hourly ground wind velocities of nearby AMeDAS, the equivalent path lengths of rain attenuation become larger as the wind directions approach the same angle to the satellite, while they become smaller as the wind directions approach the opposite angle to the satellite. The increase and decrease of the equivalent path lengths are confirmed in other Ku-band and Ka-band satellite paths with different azimuth angles, such as CS, SKP, and SBC. Modified equivalent path lengths calculated by a simple propagation path model including horizontal wind speeds along the same direction to the satellite agree well with the equivalent path lengths observed by each satellite. The equivalent path lengths are, for the first time, proved to be largely affected by the direction of typhoon passage and the horizontal wind velocities.

In this study, we develop a numerical method for determining transient energy deposition in biological bodies exposed to electromagnetic (EM) pulses. We use a newly developed frequency-dependent finite-difference time-domain (FD2TD) method, which is combined with the fast inverse Laplace transform (FILT) and Prony method. The FILT and Prony method are utilized to transform the Cole-Cole model of biological media into a sum of multiple Debye relaxation terms. Parameters of Debye terms are then extracted by comparison with the time-domain impulse responses. The extracted parameters are used in an FDTD formulation, which is derived using the auxiliary differential equation method, and transient energy deposition into a biological medium is calculated by the equivalent circuit method. The validity of our proposed method is demonstrated by comparing numerical results and those derived from an analytical method. Finally, transient energy deposition into human heads of TARO and HANAKO models is then calculated using the proposed method and, physical insights into pulse exposures of the human heads are provided.

A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic element based on the quantum flux parametron. AQFP circuits can operate with energy dissipation near the thermodynamic and quantum limits by maximizing the energy efficiency of adiabatic switching. We have established the design methodology for AQFP logic and developed various energy-efficient systems using AQFP logic, such as a low-power microprocessor, reversible computer, single-photon image sensor, and stochastic electronics. We have thus demonstrated the feasibility of the wide application of AQFP logic in future information and communications technology. In this paper, we present a tutorial review on AQFP logic to provide insights into AQFP circuit technology as an introduction to this research field. We describe the historical background, operating principle, design methodology, and recent progress of AQFP logic.

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic device. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, and several low-latency AQFP logic gates have been demonstrated. In delay-line clocking, the latency between adjacent excitation phases is determined by the propagation delay of excitation currents, and thus the rising time of excitation currents should be sufficiently small; otherwise, an AQFP gate can switch before the previous gate is fully excited. This means that delay-line clocking needs high clock frequencies, because typical excitation currents are sinusoidal and the rising time depends on the frequency. However, AQFP circuits need to be tested in a wide frequency range experimentally. Hence, in the present study, we investigate AQFP circuits adopting delay-line clocking with square excitation currents to apply delay-line clocking in a low frequency range. Square excitation currents have shorter rising time than sinusoidal excitation currents and thus enable low frequency operation. We demonstrate an AQFP buffer chain with delay-line clocking using square excitation currents, in which the latency is approximately 20ps per gate, and confirm that the operating margin for the buffer chain is kept sufficiently wide at clock frequencies below 1GHz, whereas in the sinusoidal case the operating margin shrinks below 500MHz. These results indicate that AQFP circuits adopting delay-line clocking can operate in a low frequency range by using square excitation currents.

A Josephson parametric oscillator (JPO) is an interesting system from the viewpoint of quantum optics because it has two stable self-oscillating states and can deterministically generate quantum cat states. A theoretical proposal has been made to operate a network of multiple JPOs as a quantum annealer, which can solve adiabatically combinatorial optimization problems at high speed. Proof-of-concept experiments have been actively conducted for application to quantum computations. This article provides a review of the mechanism of JPOs and their application as a quantum annealer.

We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.

In this paper, we propose a new training framework named the INmfCA algorithm for nonparallel voice conversion (VC) systems. To train conversion models, traditional VC frameworks require parallel corpora, in which source and target speakers utter the same linguistic contents. Although the frameworks have achieved high-quality VC, they are not applicable in situations where parallel corpora are unavailable. To acquire conversion models without parallel corpora, nonparallel methods are widely studied. Although the frameworks achieve VC under nonparallel conditions, they tend to require huge background knowledge or many training utterances. This is because of difficulty in disentangling linguistic and speaker information without a large amount of data. In this work, we tackle this problem by exploiting NMF, which can factorize acoustic features into time-variant and time-invariant components in an unsupervised manner. The method acquires alignment between the acoustic features of a source speaker's utterances and a target dictionary and uses the obtained alignment as activation of NMF to train the source speaker's dictionary without parallel corpora. The acquisition method is based on the INCA algorithm, which obtains the alignment of nonparallel corpora. In contrast to the INCA algorithm, the alignment is not restricted to observed samples, and thus the proposed method can efficiently utilize small nonparallel corpora. The results of subjective experiments show that the combination of the proposed algorithm and the INCA algorithm outperformed not only an INCA-based nonparallel framework but also CycleGAN-VC, which performs nonparallel VC without any additional training data. The results also indicate that a one-shot VC framework, which does not need to train source speakers, can be constructed on the basis of the proposed method.

As the basis of fine breeding management and animal husbandry insurance, individual recognition of dairy cattle is an important issue in the animal husbandry management field. Due to the limitations of the traditional method of cow identification, such as being easy to drop and falsify, it can no longer meet the needs of modern intelligent pasture management. In recent years, with the rise of computer vision technology, deep learning has developed rapidly in the field of face recognition. The recognition accuracy has surpassed the level of human face recognition and has been widely used in the production environment. However, research on the facial recognition of large livestock, such as dairy cattle, needs to be developed and improved. According to the idea of a residual network, an improved convolutional neural network (Res_5_2Net) method for individual dairy cow recognition is proposed based on dairy cow facial images in this letter. The recognition accuracy on our self-built cow face database (3012 training sets, 1536 test sets) can reach 94.53%. The experimental results show that the efficiency of identification of dairy cows is effectively improved.