The symbol basis side information generated by Viterbi's ratio threshold test technique is proposed to improve the performance of the asynchronous slow-frequency-hopped multiple access system with BFSK signaling in the frequency non-selective fading channel. By properly setting the ratio threshold to produce erasure decisions for the received symbols, the system performances are optimized. The relationship among the hit symbols in a hop duration is exploited by this symbol basis side information to greatly reduce the packet error probability. This packet error rate improvement can be as large as two order of magnitude, compared with perfect hop basis side information systems.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.

In this paper, we present a lower bound for the dimension of subfield subcodes of residue Goppa codes on the curve Cab, which exceeds the lower bound given by Stichtenoth when the number of check symbols is not small. We also give an illustrative example which shows that the proposed bound for the dimension of certain residue Goppa code exceeds the true dimension of a BCH code with the same code length and designed distance.

In this paper we propose a new far-field RCS prediction method using cylindrical or planar near-field RCS data. First we derive the relation between RCS and the scattering coefficient using physical optics technique. The far-field RCS prediction algorithm is obtained by approximating the relation using the condition of Fresnel region and the paraxial constraint of scanning angle in the case of cylindrical or planar scanning. Finally we predict the far-field RCS using measured or calculated near-field RCS data of the conducting rectangular prism or plate. The validity of the proposed algorithm is demonstrated.

The purpose of this report is to predict far-field EMI spectrum emitted from a signal line on a digital PCB based on near-field EMI measurement. The relation between near magnetic field and far electric field is shown. A method of predicting far electric field from near magnetic field is proposed. Current flowing along a signal line is calculated from measured near magnetic field. Far electric field is estimated from the current. Measurement and prediction of EM emission are carried out using a simple PCB. The result of prediction and measurement of far-field EMI spectrum coincide within the error of 3 dB.

This paper presents a method of analyzing the electromagnetic field inside an equipment housing. The electromagnetic field is assumed to be coming from outside and coupled into the housing through an aperture on the housing surface. The analysis is based on the transmission-line modeling method. Results of the analysis show a good agreement with the results of measurement. Also, it is found that the coupling through the aperture shows peaks at some frequencies that depend almost only on the structure of the housing and aperture and, therefore, can be estimated at the time of equipment design.

In the last few years analog adaptive filters have been a subject of active research because they have the ability to handle in real time much higher frequencies, with a smaller size and lower power consumption that their digital counterparts. During this time several analog adaptive filter algorithms have been reported in the literature, almost all of them use the continuous time version of the least mean square (LMS) algorithm. However the continuous time LMS algorithm presents the same limitations than its digital counterpart, when operates in noisy environments, although their convergence rate may be faster than the digital versions. This fact suggests the necessity of develop analog versions of recursive least square (RLS) algorithm, which in known to have a very low sensitivity to additive noise. However a direct implementation of the RLS in analog way would require a considerable effort. To overcome this problem, we propose an analog RLS algorithm in which the adaptive filter coefficients vector is estimated by using a fully connected network that resembles a Hopfield network. Theoretical and simulations results are given which show that the proposed and conventional RLS algorithms have quite similar convergence properties when they operate with the same sampling rate and signal-to-noise ratio.

Equivalence of physical optics (PO) and aperture field integration method (AFIM) in the full 360 observation angle is discussed for polyhedron approximate reflectors; the necessary conditions of integration surface in AFIM for the equivalence to PO are presented. In addition to the condition that complete equivalent currents consisting of both geometrical optics (GO) reflected fields from the reflector and direct incident fields from the feed source are used, the integration surface should cap the reflector perfectly and should be in the illuminated region of the GO reflected field. Validity of the conditions is numerically confirmed for a two-dimensional (2-D) strip reflector, 3-D corner reflectors and a 2-D polyhedron approximate reflector.

Switching device used on digital and inverter circuits such as a stabilizer of fluorescent lamp is one of main sources of electromagnetic noise. To make such noise characteristics clear, using a simple printed line model with a TTL IC as a switching device, electric far field noise radiating from that model is measured in an anechoic chamber. It is shown typical results and that noise characteristics can be evaluated by comparing the spectrum and spectrum change of the harmonics of 3 MHz switching pulse using the same switching device. And the characteristics of the electric field noise with PCB thickness and strip line width changed are compared with the magnetic near-field noise measured by a small shielded loop antenna. The results indicate that the electric field noise strength, on the case where the width is 7 mm and the thickness is 0.51 mm, is larger than that on other cases in the range from 50 to 150 MHz. And it is confirmed that the magnetic near-field noise increases as the loop antenna approaches the IC and varies depending on the PCB thickness and the line width. However, the spectral profile of the electric field noise is different from the magnetic near-field noise.

The approach presented in this paper was intended for extending conventional Markov random field (MRF) models to a more practical problem: the unsupervised and adaptive segmentation of gray-level images. The "unsupervised" segmentation means that all the model parameters, including the number of image classes, are unknown and have to be estimated from the observed image. In addition, the "adaptive" segmentation means that both the region distribution and the image feature within a region are all location-dependent and their corresponding parameters must be estimated from location to location. We estimated local parameters independently from multiple small windows under the assumption that an observed image consists of objects with smooth surfaces, no texture. Due to this assumption, the intensity of each region is a slowly varying function plus noise, and the conventional homogeneous hidden MRF (HMRF) models are appropriate for these windows. In each window, we employed the EM algorithm for maximum-likelihood (ML) parameter estimation, and then, the estimated parameters were used for "maximizer of the posterior marginals" (MPM) segmentation. To keep continuous segments between windows, a scheme for combining window fragments was proposed. The scheme comprises two parts: the programming of windows and the Bayesian merging of window fragments. Finally, a remerging procedure is used as post processing to remove the over-segmented small regions that possibly exist after the Bayesian merging. Since the final segments are obtained from merging, the number of image classes is automatically determined. The use of multiple parallel windows makes our algorithm to be suitable for parallel implementation. The experimental results of real-world images showed that the surfaces (objects) consistent with our reasonable model assumptions were all correctly segmented as connected regions.

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

The problem of restoring binary (black and white) images degraded by color-dependent flip-flap noises is considered. The real image is modeled by a Markov Random Field (MRF). The Iterated Conditional Modes (ICM) algorithm is adopted. It is shown that under certain conditions the ICM algorithm is insensitive to the MRF image model and noise parameters. Using this property, we propose a parameter-free restoration algorithm which does not require the estimations of the image model and noise parameters and thus can be implemented fully in parallel. The effectiveness of the proposed algorithm is shown through applying the algorithm to degraded hand-drawn and synthetic images.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

Ferroelectric / superconducting heterostructures of Pb(Zr0.52Ti0.48)O3 [PZT] / (Y0.6Pr0.4)Ba2Cu3Oy [YPBCO] have been formed on SrTiO3(100) substrate using an ArF pulsed laser deposition. The crystallinity and surface morphology of heterostructures were investigated by X-ray diffraction measurements and atomic force microscopy. We also measured dielectric and ferroelectric properties of PZT film in the Au/PZT/YPBCO structure. Furthermore, we fabricated a three-terminal devices having the structure described above using an in-situ metal mask exchange system, and investigated the ferroelectric field effect. As a result, we observed a modulation of channel resistance approximately equal to that estimated from the induced carrier and memory effect due to remanent polarization of PZT.

This paper reports the thermal stability of particulate media, which include Co-Fe oxide, CrO2, and thick and thin MP tapes. By measuring the time decay of magnetization at room temperature, fluctuation fields were obtained as a function of reverse applied field. It was clarified that the fluctuation field has a constant and minimum value when the reverse applied field is equal to coercivity. Minimum fluctuation fields for the four particulate tapes were measured at several environmental temperatures ranging from -75 to +100. It was also clarified that the fluctuation field normalized by remanence coercivity increases as the environmental temperature increases for all tapes, indicating that it is a good measure of thermal stability. Activation volumes were also deduced as a function of temperature.